Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed.
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| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer
2007
|
| Schriftenreihe: | Frontiers in electronic testing
34 |
| Schlagworte: | |
| Online-Zugang: | BTU01 Volltext |
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Datensatz im Suchindex
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| indexdate | 2024-07-09T22:05:24Z |
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| language | English |
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| series | Frontiers in electronic testing |
| series2 | Frontiers in electronic testing |
| spelling | Sachdev, Manoj Verfasser aut Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. by Manoj Sachdev and José Pineda de Gyvez Boston, MA Springer 2007 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Frontiers in electronic testing 34 Online-Ausgabe Boston, MA Springer 2007 s2007 Engineering Systems engineering Computer engineering Engineering design Electronics Circuits and Systems Electronic and Computer Engineering Electronics and Microelectronics, Instrumentation Ingenieurwissenschaften Fehlermodell (DE-588)4380447-0 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf CMOS (DE-588)4010319-5 s VLSI (DE-588)4117388-0 s Fehlermodell (DE-588)4380447-0 s Testen (DE-588)4367264-4 s DE-604 Pineda de Gyvez, José Verfasser aut Reproduktion von Sachdev, Manoj Defect-oriented testing for nano-metric CMOS VLSI circuits 2007 Frontiers in electronic testing 34 (DE-604)BV010836129 34 https://doi.org/10.1007/0-387-46547-2 Verlag Volltext |
| spellingShingle | Sachdev, Manoj Pineda de Gyvez, José Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. Frontiers in electronic testing Engineering Systems engineering Computer engineering Engineering design Electronics Circuits and Systems Electronic and Computer Engineering Electronics and Microelectronics, Instrumentation Ingenieurwissenschaften Fehlermodell (DE-588)4380447-0 gnd VLSI (DE-588)4117388-0 gnd CMOS (DE-588)4010319-5 gnd Testen (DE-588)4367264-4 gnd |
| subject_GND | (DE-588)4380447-0 (DE-588)4117388-0 (DE-588)4010319-5 (DE-588)4367264-4 |
| title | Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. |
| title_auth | Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. |
| title_exact_search | Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. |
| title_full | Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. by Manoj Sachdev and José Pineda de Gyvez |
| title_fullStr | Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. by Manoj Sachdev and José Pineda de Gyvez |
| title_full_unstemmed | Defect-oriented testing for nano-metric CMOS VLSI circuits 2. ed. by Manoj Sachdev and José Pineda de Gyvez |
| title_short | Defect-oriented testing for nano-metric CMOS VLSI circuits |
| title_sort | defect oriented testing for nano metric cmos vlsi circuits 2 ed |
| title_sub | 2. ed. |
| topic | Engineering Systems engineering Computer engineering Engineering design Electronics Circuits and Systems Electronic and Computer Engineering Electronics and Microelectronics, Instrumentation Ingenieurwissenschaften Fehlermodell (DE-588)4380447-0 gnd VLSI (DE-588)4117388-0 gnd CMOS (DE-588)4010319-5 gnd Testen (DE-588)4367264-4 gnd |
| topic_facet | Engineering Systems engineering Computer engineering Engineering design Electronics Circuits and Systems Electronic and Computer Engineering Electronics and Microelectronics, Instrumentation Ingenieurwissenschaften Fehlermodell VLSI CMOS Testen |
| url | https://doi.org/10.1007/0-387-46547-2 |
| volume_link | (DE-604)BV010836129 |
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