Fundamentals of modern VLSI devices
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| Hauptverfasser: | , |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Cambridge [u.a.]
Cambridge Univ. Press
2009
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| Ausgabe: | 2. ed. |
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| Online-Zugang: | Contributor biographical information Publisher description Table of contents only Inhaltsverzeichnis |
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| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV024629475 | ||
| 003 | DE-604 | ||
| 005 | 20151211 | ||
| 007 | t| | ||
| 008 | 090924s2009 xxkd||| |||| 00||| eng d | ||
| 020 | |a 9780521832946 |9 978-0-521-83294-6 | ||
| 020 | |a 9781107635715 |9 978-1-107-63571-5 | ||
| 035 | |a (OCoLC)268793821 | ||
| 035 | |a (DE-599)GBV593532317 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 044 | |a xxk |c XA-GB | ||
| 049 | |a DE-83 |a DE-29T | ||
| 050 | 0 | |a TK7871.99.M44 | |
| 082 | 0 | |a 621.39/5 |2 22 | |
| 084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
| 100 | 1 | |a Taur, Yuan |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Fundamentals of modern VLSI devices |c Yuan Taur ; Tak H. Ning |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a Cambridge [u.a.] |b Cambridge Univ. Press |c 2009 | |
| 300 | |a XXIII, 656 S. |b graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a Hier auch später erschienene, unverändete Nachdrucke | ||
| 500 | |a Literaturverz. S. [623] - 643 | ||
| 650 | 4 | |a Bipolar transistors | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CMOS |0 (DE-588)4010319-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a CMOS |0 (DE-588)4010319-5 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 1 | |5 DE-604 | |
| 700 | 1 | |a Ning, Tak H. |e Verfasser |4 aut | |
| 856 | 4 | |u http://www.loc.gov/catdir/enhancements/fy0906/2009007334-b.html |3 Contributor biographical information | |
| 856 | 4 | |u http://www.loc.gov/catdir/enhancements/fy0906/2009007334-d.html |3 Publisher description | |
| 856 | 4 | |u http://www.loc.gov/catdir/enhancements/fy0906/2009007334-t.html |3 Table of contents only | |
| 856 | 4 | 2 | |m GBV Datenaustausch |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018601085&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-018601085 | |
Datensatz im Suchindex
| _version_ | 1819676754870009856 |
|---|---|
| adam_text | FUNDAMENTALS OF MODERN VLSI DEVICES SECOND EDITION YUAN TAUR UNIVERSITY
OF CALIFORNIA, SAN DIEGO TAKH. NING IBM T. J. WATSON RESEARCH CENTER,
NEW YORK ** CAMBRIDGE *0 UNIVERSITY PRESS CONTENTS PREFACE TO THE
FIRST EDITION PREFACE TO THE SECOND EDITION PHYSICAL CONSTANTS AND UNIT
CONVERSIONS LIST OF SYMBOLS PAGE XI XIII XV XVI INTRODUCTION 1.1
EVOLUTION OF VLSI DEVICE TECHNOLOGY 1.1.1 HISTORICAL PERSPECTIVE 1.1.2
RECENT DEVELOPMENTS 1.2 MODERN VLSI DEVICES 1.2.1 MODERN CMOS
TRANSISTORS 1.2.2 MODERN BIPOLAR TRANSISTORS 1.3 SCOPE AND BRIEF
DESCRIPTION OF THE BOOK 1 1 4 4 4 5 6 BASIC DEVICE PHYSICS 2.1 ELECTRONS
AND HOLES IN SILICON 2.1.1 ENERGY BANDS IN SILICON 2.1.2 N-TYPE AND
P-TYPE SILICON 2.1.3 CARRIER TRANSPORT IN SILICON 2.1.4 BASIC EQUATIONS
FOR DEVICE OPERATION 2.2 P-N JUNCTIONS 2.2.1 ENERGY-BAND DIAGRAMS FOR A
P-N DIODE 2.2.2 ABRUPT JUNCTIONS 2.2.3 THE DIODE EQUATION 2.2.4
CURRENT-VOLTAGE CHARACTERISTICS 2.2.5 TIME-DEPENDENT AND SWITCHING
CHARACTERISTICS 2.2.6 DIFFUSION CAPACITANCE 2.3 MOS CAPACITORS 2.3.1
SURFACE POTENTIAL: ACCUMULATION, DEPLETION, AND INVERSION : 2.3.2
ELECTROSTATIC POTENTIAL AND CHARGE DISTRIBUTION IN SILICON 2.3.3
CAPACITANCES IN AN MOS STRUCTURE 2.3.4 POLYSILICON-GATE WORK FUNCTION
AND DEPLETION EFFECTS 2.3.5 MOS UNDER NONEQUILIBRIUM AND GATED DIODES 11
11 11 17 23 27 35 35 38 46 51 64 70 72 72 78 85 91 94 VI CONTENTS 2.3.6
CHARGE IN SILICON DIOXIDE AND AT THE SILICON-OXIDE INTERFACE 98 2.3.7
EFFECT OF INTERFACE TRAPS AND OXIDE CHARGE ON DEVICE CHARACTERISTICS 103
2.4 METAL-SILICON CONTACTS 108 2.4.1 STATIC CHARACTERISTICS OF A
SCHOTTKY BARRIER DIODE 108 2.4.2 CURRENT TRANSPORT IN A SCHOTTKY BARRIER
DIODE 115 2.4.3 CURRENT-VOLTAGE CHARACTERISTICS OF A SCHOTTKY BARRIER
DIODE 115 2.4.4 OHMIC CONTACTS 120 2.5 HIGH-FIELD EFFECTS 122 2.5.1
IMPACT IONIZATION AND AVALANCHE BREAKDOWN 122 2.5.2 BAND-TO-BAND
TUNNELING 125 2.5.3 TUNNELING INTO AND THROUGH SILICON DIOXIDE 127 2.5.4
INJECTION OF HOT CARRIERS FROM SILICON INTO SILICON DIOXIDE 133 2.5.5
HIGH-FIELD EFFECTS IN GATED DIODES 135 2.5.6 DIELECTRIC BREAKDOWN 137
EXERCISES 141 MOSFET DEVICES 148 3.1 LONG-CHANNEL MOSFETS 148 3.1.1
DRAIN-CURRENT MODEL 149 3.1.2 MOSFET I-V CHARACTERISTICS 155 3.1.3
SUBTHRESHOLD CHARACTERISTICS 163 3.1.4 SUBSTRATE BIAS AND TEMPERATURE
DEPENDENCE OF THRESHOLD VOLTAGE 166 3.1.5 MOSFET CHANNEL MOBILITY 169
3.1.6 MOSFET CAPACITANCES AND INVERSION-LAYER CAPACITANCE EFFECT 172 3.2
SHORT-CHANNEL MOSFETS 175 3.2.1 SHORT-CHANNEL EFFECT 176 3.2.2 VELOCITY
SATURATION AND HIGH-FIELD TRANSPORT 186 3.2.3 CHANNEL LENGTH MODULATION
195 3.2.4 SOURCE-DRAIN SERIES RESISTANCE 196 3.2.5 MOSFET DEGRADATION
AND BREAKDOWN AT HIGH FIELDS 196 EXERCISES 201 CMOS DEVICE DESIGN 204
4.1 MOSFET SCALING 204 4.1.1 CONSTANT-FIELD SCALING 204 4.1.2
GENERALIZED SCALING 207 4.1.3 NONSCALING EFFECTS 210 4.2 THRESHOLD
VOLTAGE 212 4.2.1 THRESHOLD-VOLTAGE REQUIREMENT 213 4.2.2 CHANNEL
PROFILE DESIGN 217 4.2.3 NONUNIFORM DOPING 224 4.2.4 QUANTUM EFFECT ON
THRESHOLD VOLTAGE 234 4.2.5 DISCRETE DOPANT EFFECTS ON THRESHOLD VOLTAGE
239 CONTENTS VII 4.3 MOSFET CHANNEL LENGTH 242 4.3.1 VARIOUS DEFINITIONS
OF CHANNEL LENGTH 242 4.3.2 EXTRACTION OF THE EFFECTIVE CHANNEL LENGTH
244 4.3.3 PHYSICAL MEANING OF EFFECTIVE CHANNEL LENGTH 248 4.3.4
EXTRACTION OF CHANNEL LENGTH BY C-V MEASUREMENTS 252 EXERCISES 254 CMOS
PERFORMANCE FACTORS 256 5.1 BASIC CMOS CIRCUIT ELEMENTS 256 5.1.1 CMOS
INVERTERS 256 5.1.2 CMOS NAND AND NOR GATES 266 5.1.3 INVERTER AND NAND
LAYOUTS 270 5.2 PARASITIC ELEMENTS 273 5.2.1 SOURCE-DRAIN RESISTANCE 274
5.2.2 PARASITIC CAPACITANCES 277 5.2.3 GATE RESISTANCE 280 5.2.4
INTERCONNECT R AND * 283 5.3 SENSITIVITY OF CMOS DELAY TO DEVICE
PARAMETERS 289 5.3.1 PROPAGATION DELAY AND DELAY EQUATION 289 5.3.2
DELAY SENSITIVITY TO CHANNEL WIDTH, LENGTH, AND GATE OXIDE THICKNESS 296
5.3.3 SENSITIVITY OF DELAY TO POWER-SUPPLY VOLTAGE AND THRESHOLD VOLTAGE
299 5.3.4 SENSITIVITY OF DELAY TO PARASITIC RESISTANCE AND CAPACITANCE
301 5.3.5 DELAY OF TWO-WAY NAND AND BODY EFFECT 304 5.4 PERFORMANCE
FACTORS OF ADVANCED CMOS DEVICES 307 5.4.1 MOSFETS IN RF CIRCUITS 308
5.4.2 EFFECT OF TRANSPORT PARAMETERS ON CMOS PERFORMANCE 311 5.4.3
LOW-TEMPERATURE CMOS 312 EXERCISES 315 BIPOLAR DEVICES 318 6.1 N-P-N
TRANSISTORS 318 6.1.1 BASIC OPERATION OF A BIPOLAR TRANSISTOR 322 6.1.2
MODIFYING THE SIMPLE DIODE THEORY FOR DESCRIBING BIPOLAR TRANSISTORS 322
6.2 IDEAL CURRENT-VOLTAGE CHARACTERISTICS 327 6.2.1 COLLECTOR CURRENT
329 6.2.2 BASE CURRENT 330 6.2.3 CURRENT GAINS 334 6.2.4 IDEAL ICV C E
CHARACTERISTICS 336 6.3 CHARACTERISTICS OF A TYPICAL N-P-N TRANSISTOR
337 6.3.1 EFFECT OF EMITTER AND BASE SERIES RESISTANCES 338 6.3.2 EFFECT
OF BASE-COLLECTOR VOLTAGE ON COLLECTOR CURRENT 340 6.3.3 COLLECTOR
CURRENT FALLOFFAT HIGH CURRENTS 343 6.3.4 NONIDEAL BASE CURRENT AT LOW
CURRENTS 347 VIII CONTENTS 6.4 BIPOLAR DEVICE MODELS FOR CIRCUIT AND
TIME-DEPENDENT ANALYSAS 352 6.4.1 BASIC DC MODEL 352 6.4.2 BASIC AC
MODEL 355 6.4.3 SMALL-SIGNAL EQUIVALENT-CIRCUIT MODEL 356 6.4.4 EMITTER
DIFFUSION CAPACITANCE 359 6.4.5 CHARGE-CONTROL ANALYSIS 361 6.5
BREAKDOWN VOLTAGES 366 6.5.1 COMMON-BASE CURRENT GAIN IN THE PRESENCE OF
BASE-COLLECTOR JUNCTION AVALANCHE 367 6.5.2 SATURATION CURRENTS IN A
TRANSISTOR 369 6.5.3 RELATION BETWEEN BV C EO AND *V CBO 370 EXERCISES
371 BIPOLAR DEVICE DESIGN 374 7.1 DESIGN OF THE EMITTER REGION 374 7.1.1
DIFFUSED OR IMPLANTED-AND-DIFFUSED EMITTER 375 7.1.2 POLYSILICON EMITTER
376 7.2 DESIGN OF THE BASE REGION 377 7.2.1 RELATIONSHIP BETWEEN BASE
SHEET RESISTIVITY AND COLLECTOR CURRENT DENSITY 378 7.2.2 INTRINSIC-BASE
DOPANT DISTRIBUTION 380 7.2.3 ELECTRIC FIELD IN THE QUASINEUTRAL
INTRINSIC BASE 381 7.2.4 BASE TRANSIT TIME 384 7.3 DESIGN OF THE
COLLECTOR REGION 385 7.3.1 COLLECTOR DESIGN WHEN THERE IS NEGLIGIBLE
BASE WIDENING 387 7.3.2 COLLECTOR DESIGN WHEN THERE IS APPRECIABLE BASE
WIDENING 388 7.4 SIGE-BASE BIPOLAR TRANSISTORS 389 7.4.1 TRANSISTORS
HAVING A SIMPLE LINEARLY GRADED BASE BANDGAP 390 7.4.2 BASE CURRENT WHEN
GE IS PRESENT IN THE EMITTER 396 7.4.3 TRANSISTORS HAVING A TRAPEZOIDAL
GE DISTRIBUTION IN THE BASE 401 7.4.4 TRANSISTORS HAVING A CONSTANT GE
DISTRIBUTION IN THE BASE 406 7.4.5 EFFECT OF EMITTER DEPTH VARIATION ON
DEVICE CHARACTERISTICS 410 7.4.6 SOME OPTIMAL GE PROFILES 414 7.4.7
BASE-WIDTH MODULATION BY V BE 419 7.4.8 REVERSE-MODE I-V CHARACTERISTICS
423 7.4.9 HETEROJUNCTION NATURE OF A SIGE-BASE BIPOLAR TRANSISTOR 426
7.5 MODERN BIPOLAR TRANSISTOR STRUCTURES 429 7.5.1 DEEP-TRENCH ISOLATION
429 7.5.2 POLYSILICON EMITTER 430 7.5.3 SELF-ALIGNED POLYSILICON BASE
CONTACT 430 7.5.4 PEDESTAL COLLECTOR 431 7.5.5 SIGE-BASE 431 EXERCISES
432 CONTENTS IX BIPOLAR PERFORMANCE FACTORS 437 8.1 FIGURES OF MERIT OF
A BIPOLAR TRANSISTOR 437 8.1.1 CUTOFF FREQUENCY 437 8.1.2 MAXIMUM
OSCILLATION FREQUENCY 440 8.1.3 RING OSCILLATOR AND GATE DELAY 440 8.2
DIGITAL BIPOLAR CIRCUITS 441 8.2.1 DELAY COMPONENTS OF A LOGIC GATE 442
8.2.2 DEVICE STRUCTURE AND LAYOUT FOR DIGITAL CIRCUITS 445 8.3 BIPOLAR
DEVICE OPTIMIZATION FOR DIGITAL CIRCUITS 447 8.3.1 DESIGN POINTS FOR A
DIGITAL CIRCUIT 447 8.3.2 DEVICE OPTIMIZATION WHEN THERE IS SIGNIFICANT
BASE WIDENING 448 8.3.3 DEVICE OPTIMIZATION WHEN THERE IS NEGLIGIBLE
BASE WIDENING 449 8.3.4 DEVICE OPTIMIZATION FOR SMALL POWER-DELAY
PRODUCT 453 8.3.5 BIPOLAR DEVICE OPTIMIZATION FROM SOME DATA ANALYSES
455 8.4 BIPOLAR DEVICE SCALING FOR ECL CIRCUITS 457 8.4.1 DEVICE SCALING
RULES 458 8.4.2 LIMITS IN BIPOLAR DEVICE SCALING FOR ECL CIRCUITS 460
8.5 BIPOLAR DEVICE OPTIMIZATION AND SCALING FOR RF AND ANALOG CIRCUITS
463 8.5.1 THE SINGLE-TRANSISTOR AMPLIFIER 463 8.5.2 OPTIMIZING THE
INDIVIDUAL PARAMETERS 464 8.5.3 TECHNOLOGY FOR RF AND ANALOG BIPOLAR
DEVICES 467 8.5.4 LIMITS IN SCALING BIPOLAR TRANSISTORS FOR RF AND
ANALOG APPLICATIONS 468 8.6 COMPARING A SIGE-BASE BIPOLAR TRANSISTOR
WITH A GAAS HBT 469 EXERCISES 472 MEMORY DEVICES 476 9.1 STATIC
RANDOM-ACCESS MEMORY 477 9.1.1 CMOS SRAM CELL 478 9.1.2 OTHER BISTABLE
MOSFET SRAM CELLS 486 9.1.3 BIPOLAR SRAM CELL 487 9.2 DYNAMIC
RANDOM-ACCESS MEMORY 495 9.2.1 BASIC DRAM CELL AND ITS OPERATION 496
9.2.2 DEVICE DESIGN AND SCALING CONSIDERATIONS FOR A DRAM CELL 499 9.3
NONVOLATILE MEMORY 500 9.3.1 MOSFET NONVOLATILE MEMORY DEVICES 501 9.3.2
FLASH MEMORY ARRAYS 507 9.3.3 FLOATING-GATE NONVOLATILE MEMORY CELLS 511
9.3.4 NONVOLATILE MEMORY CELLS WITH CHARGE STORED IN INSULATOR 514
EXERCISE 516 X CONTENTS 10 SILICON-ON-LNSULATOR DEVICES 517 10.1 SOI
CMOS 517 10.1.1 PARTIALLY DEPLETED SOI MOSFETS 518 10.1.2 FULLY DEPLETED
SOI MOSFETS 520 10.2 THIN-SILICON SOI BIPOLAR 523 10.2.1 FULLY DEPLETED
COLLECTOR MODE 524 10.2.2 PARTIALLY DEPLETED COLLECTOR MODE 526 10.2.3
ACCUMULATION COLLECTOR MODE 527 10.2.4 DISCUSSION 527 10.3 DOUBLE-GATE
MOSFETS 529 10.3.1 AN ANALYTIC DRAIN CURRENT MODEL FOR SYMMETRIC DG
MOSFETS 529 10.3.2 THE SCALE LENGTH OF DOUBLE-GATE MOSFETS 533 10.3.3
FABRICATION REQUIREMENTS AND CHALLENGES OF DG MOSFETS 534 10.3.4
MULTIPLE-GATE MOSFETS 536 EXERCISE 537 APPENDIX 1 APPENDIX 2 APPENDIX 3
APPENDIX 4 APPENDIX 5 APPENDIX * APPENDIX 7 APPENDIX 8 APPENDIX 9
APPENDIX 10 APPENDIX 11 APPENDIX 12 APPENDIX 13 APPENDIX 14 APPENDIX 15
APPENDIX 16 APPENDIX 17 APPENDIX 18 REFERENCES INDEX CMOS PROCESS FLOW
OUTLINE OF A PROCESS FOR FABRICATING MODERN N-P-N BIPOLAR TRANSISTORS
EINSTEIN RELATIONS SPATIAL VARIATION OF QUASI-FERMI POTENTIALS
GENERATION AND RECOMBINATION PROCESSES AND SPACE-CHARGE- REGION CURRENT
DIFFUSION CAPACITANCE OF A P-N DIODE IMAGE-FORCE-INDUCED BARRIER
LOWERING ELECTRON-INITIATED AND HOLE-INITIATED AVALANCHE BREAKDOWN AN
ANALYTICAL SOLUTION FOR THE SHORT-CHANNEL EFFECT IN SUBTHRESHOLD
GENERALIZED MOSFET SCALE LENGTH MODEL DRAIN CURRENT MODEL OF A BALLISTIC
MOSFET QUANTUM-MECHANICAL SOLUTION IN WEAK INVERSION POWER GAIN OF A
TWO-PORT NETWORK UNITY-GAIN FREQUENCIES OF A MOSFET TRANSISTOR
DETERMINATION OF EMITTER AND BASE SERIES RESISTANCES INTRINSIC-BASE
RESISTANCE ENERGY-BAND DIAGRAM OF A SI-SIGE N-P DIODE J/^AND^NAX OF A
BIPOLAR TRANSISTOR 538 542 543 546 553 562 569 573 575 582 588 594 598
601 605 610 614 617 623 644
|
| any_adam_object | 1 |
| author | Taur, Yuan Ning, Tak H. |
| author_facet | Taur, Yuan Ning, Tak H. |
| author_role | aut aut |
| author_sort | Taur, Yuan |
| author_variant | y t yt t h n th thn |
| building | Verbundindex |
| bvnumber | BV024629475 |
| callnumber-first | T - Technology |
| callnumber-label | TK7871 |
| callnumber-raw | TK7871.99.M44 |
| callnumber-search | TK7871.99.M44 |
| callnumber-sort | TK 47871.99 M44 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4952 |
| ctrlnum | (OCoLC)268793821 (DE-599)GBV593532317 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 2. ed. |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02183nam a2200541 c 4500</leader><controlfield tag="001">BV024629475</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20151211 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">090924s2009 xxkd||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780521832946</subfield><subfield code="9">978-0-521-83294-6</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781107635715</subfield><subfield code="9">978-1-107-63571-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)268793821</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)GBV593532317</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="044" ind1=" " ind2=" "><subfield code="a">xxk</subfield><subfield code="c">XA-GB</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-83</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7871.99.M44</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Taur, Yuan</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Fundamentals of modern VLSI devices</subfield><subfield code="c">Yuan Taur ; Tak H. Ning</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge [u.a.]</subfield><subfield code="b">Cambridge Univ. Press</subfield><subfield code="c">2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XXIII, 656 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Hier auch später erschienene, unverändete Nachdrucke</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Literaturverz. S. [623] - 643</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Bipolar transistors</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ning, Tak H.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0906/2009007334-b.html</subfield><subfield code="3">Contributor biographical information</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0906/2009007334-d.html</subfield><subfield code="3">Publisher description</subfield></datafield><datafield tag="856" ind1="4" ind2=" "><subfield code="u">http://www.loc.gov/catdir/enhancements/fy0906/2009007334-t.html</subfield><subfield code="3">Table of contents only</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">GBV Datenaustausch</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018601085&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-018601085</subfield></datafield></record></collection> |
| id | DE-604.BV024629475 |
| illustrated | Illustrated |
| indexdate | 2024-12-23T22:41:49Z |
| institution | BVB |
| isbn | 9780521832946 9781107635715 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-018601085 |
| oclc_num | 268793821 |
| open_access_boolean | |
| owner | DE-83 DE-29T |
| owner_facet | DE-83 DE-29T |
| physical | XXIII, 656 S. graph. Darst. |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | Cambridge Univ. Press |
| record_format | marc |
| spellingShingle | Taur, Yuan Ning, Tak H. Fundamentals of modern VLSI devices Bipolar transistors Integrated circuits Very large scale integration Metal oxide semiconductors, Complementary VLSI (DE-588)4117388-0 gnd CMOS (DE-588)4010319-5 gnd Entwurf (DE-588)4121208-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4010319-5 (DE-588)4121208-3 |
| title | Fundamentals of modern VLSI devices |
| title_auth | Fundamentals of modern VLSI devices |
| title_exact_search | Fundamentals of modern VLSI devices |
| title_full | Fundamentals of modern VLSI devices Yuan Taur ; Tak H. Ning |
| title_fullStr | Fundamentals of modern VLSI devices Yuan Taur ; Tak H. Ning |
| title_full_unstemmed | Fundamentals of modern VLSI devices Yuan Taur ; Tak H. Ning |
| title_short | Fundamentals of modern VLSI devices |
| title_sort | fundamentals of modern vlsi devices |
| topic | Bipolar transistors Integrated circuits Very large scale integration Metal oxide semiconductors, Complementary VLSI (DE-588)4117388-0 gnd CMOS (DE-588)4010319-5 gnd Entwurf (DE-588)4121208-3 gnd |
| topic_facet | Bipolar transistors Integrated circuits Very large scale integration Metal oxide semiconductors, Complementary VLSI CMOS Entwurf |
| url | http://www.loc.gov/catdir/enhancements/fy0906/2009007334-b.html http://www.loc.gov/catdir/enhancements/fy0906/2009007334-d.html http://www.loc.gov/catdir/enhancements/fy0906/2009007334-t.html http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018601085&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT tauryuan fundamentalsofmodernvlsidevices AT ningtakh fundamentalsofmodernvlsidevices |