Simulating synchronous processors
This paper shows how a distributed system with synchronous processors and asynchronous message delays can be simulated by a system with both asynchronous processors and asynchronous message delays in the presence of various types of processor faults. Consequently, the result of Fischer, Lynch and Pa...
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Cambridge, Mass.
Mass. Inst. of Technology, Laboratory for Computer Science
1988
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| 100 | 1 | |a Welch, Jennifer Lundelius |e Verfasser |0 (DE-588)1089587988 |4 aut | |
| 245 | 1 | 0 | |a Simulating synchronous processors |c Jennifer Lundelius Welch |
| 264 | 1 | |a Cambridge, Mass. |b Mass. Inst. of Technology, Laboratory for Computer Science |c 1988 | |
| 300 | |a 15 S. | ||
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| 337 | |b n |2 rdamedia | ||
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| 520 | 3 | |a This paper shows how a distributed system with synchronous processors and asynchronous message delays can be simulated by a system with both asynchronous processors and asynchronous message delays in the presence of various types of processor faults. Consequently, the result of Fischer, Lynch and Paterson (1985), that no consensus protocol for asynchronous processors and communication can tolerate one failstop fault, implies a result of Dolev, Dwork and Stockmeyer (1987), that no concensus protocol for synchronous processors and asynchronous communication can tolerate one failstop fault. Keywords: Fault tolerance, Simulation. (KR). | |
| 650 | 7 | |a Asynchronous computers |2 dtict | |
| 650 | 7 | |a Communication and radio systems |2 dtict | |
| 650 | 7 | |a Computer Hardware |2 scgdst | |
| 650 | 7 | |a Computerized simulation |2 dtict | |
| 650 | 7 | |a Delay |2 dtict | |
| 650 | 7 | |a Fault tolerant computing |2 dtict | |
| 650 | 7 | |a Message processing |2 dtict | |
| 650 | 7 | |a Processing equipment |2 dtict | |
| 650 | 0 | 7 | |a Simulation |0 (DE-588)4055072-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Fehlertoleranz |0 (DE-588)4123192-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Verteiltes Datenbanksystem |0 (DE-588)4121865-6 |2 gnd |9 rswk-swf |
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| 689 | 0 | 1 | |a Fehlertoleranz |0 (DE-588)4123192-2 |D s |
| 689 | 0 | 2 | |a Simulation |0 (DE-588)4055072-2 |D s |
| 689 | 0 | |5 DE-604 | |
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Datensatz im Suchindex
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| author | Welch, Jennifer Lundelius |
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| bvnumber | BV021892003 |
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Consequently, the result of Fischer, Lynch and Paterson (1985), that no consensus protocol for asynchronous processors and communication can tolerate one failstop fault, implies a result of Dolev, Dwork and Stockmeyer (1987), that no concensus protocol for synchronous processors and asynchronous communication can tolerate one failstop fault. Keywords: Fault tolerance, Simulation. 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| id | DE-604.BV021892003 |
| illustrated | Not Illustrated |
| index_date | 2024-07-02T16:04:12Z |
| indexdate | 2024-07-09T20:46:49Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015107201 |
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| owner_facet | DE-706 |
| physical | 15 S. |
| publishDate | 1988 |
| publishDateSearch | 1988 |
| publishDateSort | 1988 |
| publisher | Mass. Inst. of Technology, Laboratory for Computer Science |
| record_format | marc |
| spelling | Welch, Jennifer Lundelius Verfasser (DE-588)1089587988 aut Simulating synchronous processors Jennifer Lundelius Welch Cambridge, Mass. Mass. Inst. of Technology, Laboratory for Computer Science 1988 15 S. txt rdacontent n rdamedia nc rdacarrier This paper shows how a distributed system with synchronous processors and asynchronous message delays can be simulated by a system with both asynchronous processors and asynchronous message delays in the presence of various types of processor faults. Consequently, the result of Fischer, Lynch and Paterson (1985), that no consensus protocol for asynchronous processors and communication can tolerate one failstop fault, implies a result of Dolev, Dwork and Stockmeyer (1987), that no concensus protocol for synchronous processors and asynchronous communication can tolerate one failstop fault. Keywords: Fault tolerance, Simulation. (KR). Asynchronous computers dtict Communication and radio systems dtict Computer Hardware scgdst Computerized simulation dtict Delay dtict Fault tolerant computing dtict Message processing dtict Processing equipment dtict Simulation (DE-588)4055072-2 gnd rswk-swf Fehlertoleranz (DE-588)4123192-2 gnd rswk-swf Verteiltes Datenbanksystem (DE-588)4121865-6 gnd rswk-swf Verteiltes Datenbanksystem (DE-588)4121865-6 s Fehlertoleranz (DE-588)4123192-2 s Simulation (DE-588)4055072-2 s DE-604 |
| spellingShingle | Welch, Jennifer Lundelius Simulating synchronous processors Asynchronous computers dtict Communication and radio systems dtict Computer Hardware scgdst Computerized simulation dtict Delay dtict Fault tolerant computing dtict Message processing dtict Processing equipment dtict Simulation (DE-588)4055072-2 gnd Fehlertoleranz (DE-588)4123192-2 gnd Verteiltes Datenbanksystem (DE-588)4121865-6 gnd |
| subject_GND | (DE-588)4055072-2 (DE-588)4123192-2 (DE-588)4121865-6 |
| title | Simulating synchronous processors |
| title_auth | Simulating synchronous processors |
| title_exact_search | Simulating synchronous processors |
| title_exact_search_txtP | Simulating synchronous processors |
| title_full | Simulating synchronous processors Jennifer Lundelius Welch |
| title_fullStr | Simulating synchronous processors Jennifer Lundelius Welch |
| title_full_unstemmed | Simulating synchronous processors Jennifer Lundelius Welch |
| title_short | Simulating synchronous processors |
| title_sort | simulating synchronous processors |
| topic | Asynchronous computers dtict Communication and radio systems dtict Computer Hardware scgdst Computerized simulation dtict Delay dtict Fault tolerant computing dtict Message processing dtict Processing equipment dtict Simulation (DE-588)4055072-2 gnd Fehlertoleranz (DE-588)4123192-2 gnd Verteiltes Datenbanksystem (DE-588)4121865-6 gnd |
| topic_facet | Asynchronous computers Communication and radio systems Computer Hardware Computerized simulation Delay Fault tolerant computing Message processing Processing equipment Simulation Fehlertoleranz Verteiltes Datenbanksystem |
| work_keys_str_mv | AT welchjenniferlundelius simulatingsynchronousprocessors |