Routing the power and ground wires on a VLSI chip
This thesis presents four new algorithms to route noncrossing power and ground trees in one metal layer of a VLSI chip. The implementation of the best algorithm forms MIT's Placement-Interconnect (PI) Projects power-ground routing phase. The input of this power-ground algorithm is a set of rect...
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Cambridge, Mass.
Mass. Inst. of Technology, Laboratory for Computer Science
1984
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| 100 | 1 | |a Moulton, Andrew S. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Routing the power and ground wires on a VLSI chip |c by Andrew Strout Moulton |
| 264 | 1 | |a Cambridge, Mass. |b Mass. Inst. of Technology, Laboratory for Computer Science |c 1984 | |
| 300 | |a 66 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 520 | 3 | |a This thesis presents four new algorithms to route noncrossing power and ground trees in one metal layer of a VLSI chip. The implementation of the best algorithm forms MIT's Placement-Interconnect (PI) Projects power-ground routing phase. The input of this power-ground algorithm is a set of rectangular modules on a rectangular chip. Because of bonding limitations, the pads are placed along the chip's perimeter, while the logic modules are placed in the interior. In constructing the power-ground layout, the algorithm first lays a ground ring between the pads and the chip's perimeter, then a power ring between the logic modules and the pads. Next, a tree of wires connects the ground pad with the logic modules' ground connection points. Then, starting at various points on the power ring, several branches of wires connect the power ring to the logic modules' power connection points. A tree-traversal algorithm then uses the modules' current requirements to determine how much current will flow through each power-ground wire during the chip's operation. An algorithm then widens each wire to the width appropriate for carrying that current. (Author). | |
| 650 | 7 | |a Algorithms |2 dtict | |
| 650 | 7 | |a Chips(electronics) |2 dtict | |
| 650 | 7 | |a Circuit interconnections |2 dtict | |
| 650 | 7 | |a Computer aided design |2 dtict | |
| 650 | 7 | |a Electrical and Electronic Equipment |2 scgdst | |
| 650 | 7 | |a Electrical grounding |2 dtict | |
| 650 | 7 | |a Graphs |2 dtict | |
| 650 | 7 | |a Integrated systems |2 dtict | |
| 650 | 7 | |a Modules(electronics) |2 dtict | |
| 650 | 7 | |a Routing |2 dtict | |
| 650 | 7 | |a Theses |2 dtict | |
| 650 | 7 | |a Wire |2 dtict | |
| 650 | 0 | 7 | |a Entwurfsautomation |0 (DE-588)4312536-0 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
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| author | Moulton, Andrew S. |
| author_facet | Moulton, Andrew S. |
| author_role | aut |
| author_sort | Moulton, Andrew S. |
| author_variant | a s m as asm |
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| bvnumber | BV021891496 |
| ctrlnum | (OCoLC)227623793 (DE-599)BVBBV021891496 |
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Because of bonding limitations, the pads are placed along the chip's perimeter, while the logic modules are placed in the interior. In constructing the power-ground layout, the algorithm first lays a ground ring between the pads and the chip's perimeter, then a power ring between the logic modules and the pads. Next, a tree of wires connects the ground pad with the logic modules' ground connection points. Then, starting at various points on the power ring, several branches of wires connect the power ring to the logic modules' power connection points. A tree-traversal algorithm then uses the modules' current requirements to determine how much current will flow through each power-ground wire during the chip's operation. An algorithm then widens each wire to the width appropriate for carrying that current. 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| id | DE-604.BV021891496 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-23T19:46:24Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-015106696 |
| oclc_num | 227623793 |
| open_access_boolean | |
| owner | DE-706 |
| owner_facet | DE-706 |
| physical | 66 S. |
| publishDate | 1984 |
| publishDateSearch | 1984 |
| publishDateSort | 1984 |
| publisher | Mass. Inst. of Technology, Laboratory for Computer Science |
| record_format | marc |
| spelling | Moulton, Andrew S. Verfasser aut Routing the power and ground wires on a VLSI chip by Andrew Strout Moulton Cambridge, Mass. Mass. Inst. of Technology, Laboratory for Computer Science 1984 66 S. txt rdacontent n rdamedia nc rdacarrier This thesis presents four new algorithms to route noncrossing power and ground trees in one metal layer of a VLSI chip. The implementation of the best algorithm forms MIT's Placement-Interconnect (PI) Projects power-ground routing phase. The input of this power-ground algorithm is a set of rectangular modules on a rectangular chip. Because of bonding limitations, the pads are placed along the chip's perimeter, while the logic modules are placed in the interior. In constructing the power-ground layout, the algorithm first lays a ground ring between the pads and the chip's perimeter, then a power ring between the logic modules and the pads. Next, a tree of wires connects the ground pad with the logic modules' ground connection points. Then, starting at various points on the power ring, several branches of wires connect the power ring to the logic modules' power connection points. A tree-traversal algorithm then uses the modules' current requirements to determine how much current will flow through each power-ground wire during the chip's operation. An algorithm then widens each wire to the width appropriate for carrying that current. (Author). Algorithms dtict Chips(electronics) dtict Circuit interconnections dtict Computer aided design dtict Electrical and Electronic Equipment scgdst Electrical grounding dtict Graphs dtict Integrated systems dtict Modules(electronics) dtict Routing dtict Theses dtict Wire dtict Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Algorithmus (DE-588)4001183-5 s DE-604 Entwurfsautomation (DE-588)4312536-0 s |
| spellingShingle | Moulton, Andrew S. Routing the power and ground wires on a VLSI chip Algorithms dtict Chips(electronics) dtict Circuit interconnections dtict Computer aided design dtict Electrical and Electronic Equipment scgdst Electrical grounding dtict Graphs dtict Integrated systems dtict Modules(electronics) dtict Routing dtict Theses dtict Wire dtict Entwurfsautomation (DE-588)4312536-0 gnd Algorithmus (DE-588)4001183-5 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)4001183-5 |
| title | Routing the power and ground wires on a VLSI chip |
| title_auth | Routing the power and ground wires on a VLSI chip |
| title_exact_search | Routing the power and ground wires on a VLSI chip |
| title_full | Routing the power and ground wires on a VLSI chip by Andrew Strout Moulton |
| title_fullStr | Routing the power and ground wires on a VLSI chip by Andrew Strout Moulton |
| title_full_unstemmed | Routing the power and ground wires on a VLSI chip by Andrew Strout Moulton |
| title_short | Routing the power and ground wires on a VLSI chip |
| title_sort | routing the power and ground wires on a vlsi chip |
| topic | Algorithms dtict Chips(electronics) dtict Circuit interconnections dtict Computer aided design dtict Electrical and Electronic Equipment scgdst Electrical grounding dtict Graphs dtict Integrated systems dtict Modules(electronics) dtict Routing dtict Theses dtict Wire dtict Entwurfsautomation (DE-588)4312536-0 gnd Algorithmus (DE-588)4001183-5 gnd |
| topic_facet | Algorithms Chips(electronics) Circuit interconnections Computer aided design Electrical and Electronic Equipment Electrical grounding Graphs Integrated systems Modules(electronics) Routing Theses Wire Entwurfsautomation Algorithmus |
| work_keys_str_mv | AT moultonandrews routingthepowerandgroundwiresonavlsichip |