Integrated circuit design for high-speed frequency synthesis
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| Format: | Buch |
| Sprache: | English |
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Boston [u.a.]
Artech House
2006
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| Schriftenreihe: | Artech House microwave library
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| 100 | 1 | |a Rogers, John W. M. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Integrated circuit design for high-speed frequency synthesis |c John Rogers, Calvin Plett, Foster Dai |
| 264 | 1 | |a Boston [u.a.] |b Artech House |c 2006 | |
| 300 | |a xiii, 478 S. |b graph. Darst. |c 26 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Artech House microwave library | |
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Circuits intégrés à très grande vitesse - Conception et construction | |
| 650 | 4 | |a Very high speed integrated circuits |x Design and construction | |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
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| 700 | 1 | |a Dai, Foster |e Verfasser |4 aut | |
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Datensatz im Suchindex
| _version_ | 1819585413117902848 |
|---|---|
| adam_text | INTEGRATED CIRCUIT DESIGN FOR HIGH-SPEED FREQUENCY SYNTHESIS JOHN ROGERS
CALVIN PLETT FOSTER DAI ARTECH H O US E BOSTON|LONDON ARTECHHOUSE.COM
PREFACE XI CHAPTER 1 INTRODUCTION 1 1.1 INTRODUCTION TO FREQUENCY
SYNTHESIS 1 1.2 FREQUENCY SYNTHESIS FOR TELECOMMUNICATIONS SYSTEMS 1 1.3
FREQUENCY SYNTHESIS FOR DIGITAL CIRCUIT APPLICATIONS 5 1.4 FREQUENCY
SYNTHESIS FOR CLOCK AND DATA RECOVERY 8 1.5 FREQUENCY SYNTHESIS FOR
MODULATION AND WAVEFORM GENERATION 11 1.6 OVERVIEW 13 REFERENCES 14
CHAPTER 2 SYNTHESIZER ARCHITECTURES 1 7 2.1 INTRODUCTION YJ 2.2
INTEGER-N PLL SYNTHESIZERS 17 2.3 FRACTIONAL-N PLL FREQUENCY
SYNTHESIZERS 18 2.3.1 FRACTIONAL-N SYNTHESIZER WITH DUAL-MODULUS
PRESCALER 19 2.3.2 AN ACCUMULATOR WITH PROGRAMMABLE SIZE 21 2.3.3
FRACTIONAL-N SYNTHESIZER WITH MULTIMODULUS DIVIDER 23 2.3.4 FRACTIONAL-N
SPURIOUS COMPONENTS 24 2.4 DELAY-LOCKED LOOPS 27 2.5 CLOCK AND DATA
RECOVERY (CDR) PLLS 29 2.6 DIRECT DIGITAL SYNTHESIZERS 31 2.6.1 DIRECT
DIGITAL SYNTHESIZER WITH READ-ONLY MEMORY LOOKUP TABLE 32 2.6.2 ROM-LESS
DIRECT DIGITAL SYNTHESIZER 33 2.7 DIRECT ANALOG FREQUENCY SYNTHESIZERS
33 2.8 HYBRID FREQUENCY SYNTHESIZERS 34 REFERENCES 3 G CHAPTER3
SYSTEM-LEVEL OVERVIEW OF PLL-BASED FREQUENCY SYNTHESIS 43 3.1
INTRODUCTION 43 3.2 PLLS (EXAMPLE OF A FEEDBACK SYSTEM) 43 3.3 PLL
COMPONENTS 44 3.3.1 VCOS AND DIVIDERS 44 3.3.2 PHASE DETECTORS 4G 3.3.3
THE LOOP FILTER 51 CONTENTS 3.4 CONTINUOUS-TIME ANALYSIS FOR PLL
SYNTHESIZERS 52 3.4.1 SIMPLIFIED LOOP EQUATIONS 53 3.4.2 PLL SYSTEM
FREQUENCY RESPONSE AND BANDWIDTH 55 3.4.3 COMPLETE LOOP TRANSFER
FUNCTION, INCLUDING C2 56 3.5 DISCRETE-TIME ANALYSIS FOR PLL
SYNTHESIZERS 58 3.6 TRANSIENT BEHAVIOR OF PLLS 61 3.6.1 LINEAR TRANSIENT
BEHAVIOR 62 3.6.2 NONLINEAR TRANSIENT BEHAVIOR 66 3.7 PHASE NOISE AND
TIMING JITTER IN PLL SYNTHESIS 71 3.7.1 VARIOUS NOISE SOURCES IN PLL
SYNTHESIZERS 75 3.7.2 IN-BAND AND OUT-OF-BAND PHASE NOISE IN PLL
SYNTHESIS 78 REFERENCES 83 CHAPTER 4 INTRODUCTION TO DIGITAL IC DESIGN
85 4.1 DIGITAL DESIGN METHODOLOGY AND FLOW 85 4.2 VERILOGHDL 88 4.2.1
VERILOG PROGRAM STRUCTURE 89 4.2.2 VERILOG DATA FORMATS 94 4.2.3 VERILOG
OPERATORS 95 4.2.4 VERILOG CONTROL CONSTRUCTS 95 4.2.5 BLOCKING AND
NONBLOCKING ASSIGNMENTS 97 4.2.6 TASKS AND FUNCTIONS 99 4.3 BEHAVIORAL
AND STRUCTURAL MODELING 101 4.4 COMBINATIONAL DIGITAL CIRCUIT DESIGN 102
4.5 SEQUENTIAL DIGITAL CIRCUIT DESIGN 103 4.6 DIGITAL DESIGN EXAMPLE I:
A MULTIMODULUS DIVIDER 106 4.7 DIGITAL DESIGN EXAMPLE II: A PROGRAMMABLE
MASH A2 MODULATOR 109 4.7.1 MASH SA MODULATOR TOP-LEVEL STRUCTURE 110
4.7.2 FRACTIONAL ACCUMULATOR WITH PROGRAMMABLE SIZE AND SEED- LOADING
CAPABILITY 114 4.7.3 RESET SYNCHRONIZATION 116 4.7.4 SIMULATED RESULTS
117 REFERENCES 118 CHAPTER 5 CMOS LOGIC AND CURRENT MODE LOGIC 119 5.1
INTRODUCTION 119 5.2 CMOS LOGIC CIRCUITS 120 5.3 LARGE-SIGNAL BEHAVIOR
OF BIPOLAR AND CMOS DIFFERENTIAL PAIRS 121 5.4 EFFECT OF CAPACITANCE ON
SLEW RATE 125 5.5 TRADE-OFF BETWEEN POWER CONSUMPTION AND SPEED 129 5.6
CML COMBINATIONAL CIRCUITS 132 5.7 CML SEQUENTIAL CIRCUITS 134 5.8
MASTER-SLAVE D -FLIP-FLOP 139 5.9 CML CIRCUIT-DELAY ANALYSIS 142
CONTENTS VII 5.10 LOW-POWER CML CIRCUITS 144 5.11 CML BIASING CIRCUITS
146 5.12 DRIVER CIRCUITS 150 REFERENCES 152 CHAPTER 6 DIVIDERS AND
PHASE-FREQUENCY DETECTORS 153 6.1 INTRODUCTION 153 6.2 DIVIDERS 153
6.2.1 A STATIC DIVIDE-BY-TWO CIRCUIT 155 6.2.2 PROGRAMMABLE
DIVIDE-BY-TWO OR DIVIDE-BY-THREE CIRCUIT 158 6.2.3 A 50% DUTY CYCLE,
HIGH-SPEED, DIVIDE-BY-THREE CIRCUIT 163 6.2.4 A MULTIMODULUS DIVIDER 165
6.2.5 A GENERIC MMD ARCHITECTURE 170 6.2.6 PULSE-SWALLOW DIVIDERS 175
6.3 MULTIPLIERS 180 6.4 PHASE DETECTORS 181 6.4.1 BASIC TYPES OF PHASE
DETECTORS 181 6.4.2 CIRCUIT IMPLEMENTATIONS OF PFDS 183 6.4.3 DEAD ZONE
IN PFDS 186 6.4.4 LOCK-DETECTION CIRCUITS 189 6.4.5 A MODIFIED PFD WITH
ALIGNED UP AND DN PULSES 190 6.4.6 PFDS FOR CDR APPLICATIONS 191
REFERENCES 196 CHAPTER 7 CHARGE PUMPS AND LOOP FILTERS 199 7.1
INTRODUCTION 199 7.2 CHARGE PUMPS 199 7.2.1 A BASIC CHARGE PUMP 199
7.2.2 SATURATION VOLTAGE 200 7.2.3 CURRENT SOURCE OUTPUT IMPEDANCE 201
7.2.4 REFERENCE FEEDTHROUGH 203 7.2.5 TRANSISTOR GAIN CONSIDERATIONS 206
7.2.6 CHARGE PUMP NOISE 207 7.2.7 CHARGE SHARING 209 7.2.8 IMPROVING
MATCHING BETWEEN IP AND I N 209 7.2.9 CHARGE PUMPS COMPATIBLE WITH
CML/ECL 211 7.2.10 A DIFFERENTIAL CHARGE PUMP 215 7.2.11 COMMON-MODE
FEEDBACK FOR A DIFFERENTIAL CHARGE PUMP 217 7.2.12 ANOTHER DIFFERENTIAL
CHARGE PUMP 217 7.2.13 PROGRAMMABLE BIAS SCHEMES 218 7.3 LOOP FILTERS
218 7.3.1 PASSIVE LOOP FILTERS 219 7.3.2 ACTIVE LOOP FILTERS 222 7.3.3
LC LOOP FILTERS 224 REFERENCES 230 VIII CONTENTS CHAPTER 8
VOLTAGE-CONTROLLED OSCILLATORS 233 8.1 INTRODUCTION 233 8.2
SPECIFICATION OF OSCILLATOR PROPERTIES 233 8.3 LC-BASED VCOS 233 8.3.1
INDUCTORS 234 8.3.2 VARACTORS FOR OSCILLATOR FREQUENCY CONTROL 238 8.4
OSCILLATOR ANALYSIS 241 8.4.1 COLPITTS OSCILLATOR ANALYSIS 242 8.4.2
NEGATIVE RESISTANCE OF -G M OSCILLATOR 244 8.5 AMPLITUDE OF A NEGATIVE G
M OSCILLATOR 244 8.6 SEVERAL REFINEMENTS TO THE -G M TOPOLOGY 245 8.7
INJECTION-LOCKED OSCILLATORS 246 8.7.1 PHASE SHIFT OF INJECTION-LOCKED
OSCILLATOR 254 8.8 QUADRATURE LC OSCILLATORS USING INJECTION LOCKING 257
8.8.1 PARALLEL COUPLED QUADRATURE LC OSCILLATORS 258 8.8.2 SERIES
COUPLED QUADRATURE OSCILLATORS 263 8.8.3 OTHER QUADRATURE-GENERATION
TECHNIQUES 263 8.9 OTHER TECHNIQUES TO GENERATE QUADRATURE SIGNALS 264
8.10 PHASE NOISE IN LC OSCILLATORS 264 8.10.1 LINEAR OR ADDITIVE PHASE
NOISE AND LEESON S FORMULA 265 8.10.2 SWITCHING PHASE NOISE IN
CROSS-COUPLED PAIRS 269 8.11 LOW-FREQUENCY PHASE NOISE UPCONVERSION
REDUCTION TECHNIQUES 270 8.11.1 BANK SWITCHING 270 8.11.2 G M MATCHING
AND WAVEFORM SYMMETRY 272 8.11.3 DIFFERENTIAL VARACTORS AND DIFFERENTIAL
TUNING 273 8.12 RING OSCILLATORS 276 8.13 COMMON INVERTER CIRCUITS 281
8.14 METHOD FOR DESIGNING A TWO-STAGE RING OSCILLATOR 284 8.15 PHASE
NOISE AND JITTER IN RING OSCILLATORS 287 8.16 CRYSTAL OSCILLATORS 294
8.17 SUMMARY: COMPARISON OF OSCILLATOR PERFORMANCE 298 REFERENCES 299
CHAPTER 9 SA MODULATION FOR FRACTIONAL-N SYNTHESIS 301 9.1 INTRODUCTION
301 9.2 BASIC CONCEPTS 301 9.2.1 QUANTIZATION NOISE AND OVERSAMPLING
EFFECTS 301 9.2.2 NOISE-SHAPING EFFECT 306 9.2.3 AN OVERVIEW OF SA
MODULATORS 308 9.2.4 FIRST-ORDER SA MODULATORS 309 9.2.5 SECOND-ORDER SA
MODULATORS 311 9.2.6 HIGH-ORDER SA MODULATORS 312 IX 9.3 SA MODULATION
IN FRACTIONAL-N FREQUENCY SYNTHESIS 315 9.3.1 A FIRST-ORDER SA MODULATOR
FOR FRACTIONAL-N FREQUENCY SYNTHESIS 317 9.3.2 MASH SA MODULATOR 319
9.3.3 SINGLE-STAGE SA MODULATORS WITH MULTIPLE FEEDBACK PATHS 326 9.3.4
SINGLE-STAGE SA MODULATORS WITH A SINGLE FEEDBACK PATH 327 9.3.5 A
GENERIC HIGH-ORDER SA MODULATOR TOPOLOGY 330 9.3.6 MODIFIED SA MODULATOR
WITH IMPROVED HIGH-FREQUENCY RESPONSE 338 9.3.7 PHASE NOISE DUE TO SA
CONVERTERS 342 9.3.8 RANDOMIZATION BY NOISE-SHAPED DITHERING 347 9.3.9
SPUR REDUCTION USING PRECALCULATED SEEDS 349 9.3.10 DYNAMIC RANGE 349
9.3.11 MAXIMAL LOOP BANDWIDTH 352 9.3.12 OPTIMAL PARAMETERS 354 9.3.13
PERFORMANCE COMPARISON 355 REFERENCES 356 CHARTER 10 DIRECT DIGITAL
SYNTHESIS 359 10.1 INTRODUCTION 359 10.2 DDS THEORY OF OPERATION 360
10.3 DDS SPECTRAL PURITY 363 10.3.1 PHASE NOISE DUE TO CLOCK JITTER 364
10.3.2 SPURS DUE TO DISCRETE PHASE ACCUMULATION 365 10.3.3 SPURS AND
QUANTIZATION NOISE DUE TO PHASE TRUNCATION 367 10.3.4 QUANTIZATION NOISE
DUE TO FINITE NUMBER OF AMPLITUDE BITS 373 10.3.5 DAC NONLINEARITIES AND
ALIASED IMAGES 374 10.3.6 OVERSAMPLING EFFECT 376 10.4 SA NOISE SHAPING
IN DDS 376 10.4.1 DDS USING PHASE DOMAIN SA NOISE SHAPING 377 10.4.2 DDS
USING FREQUENCY DOMAIN SA NOISE SHAPING 379 10.4.3 ROM SIZE REDUCTION
USING SA NOISE SHAPING 379 10.5 HIGH-SPEED ROM-LESS DDS 381 10.5.1
PIPELINED ACCUMULATOR 383 10.5.2 ACCUMULATOR WITH CLA ADDERS 384 10.5.3
SINE-WEIGHTED NONLINEAR DACS 388 10.5.4 NONLINEAR DAC SEGMENTATIONS 389
10.5.5 NONLINEAR COARSE DAC 391 10.5.6 COMPARISON OF ROM-LESS DDS
PERFORMANCE 394 REFERENCES 395 CHAPTER11 DIRECT MODULATION IN FREQUENCY
SYNTHESIZERS 397 11.1 INTRODUCTION 397 11.2 DIRECT MODULATION IN PLL
FREQUENCY SYNTHESIZERS 398 X CONTENTS 11.3 DIRECT DIGITAL MODULATION AND
WAVEFORM GENERATION IN A DDS 401 11.3.1 PHASE MODULATION 403 11.3.2
PHASE SHIFT KEYING 403 11.3.3 FREQUENCY MODULATION 407 11.3.4 MINIMUM
SHIFT KEYING 411 11.3.5 STEP FREQUENCY 412 11.3.6 CHIRP WAVEFORMS 412
11.3.7 AMPLITUDE MODULATION 413 11.3.8 QUADRATURE AMPLITUDE MODULATION
413 11.3.9 WAVEFORM GENERATION 414 REFERENCES 415 APPENDIX A A REVIEW OF
BASIC CONTROL THEORY 417 A.L INTRODUCTION 417 A.2 THE CONTINUOUS-TIME
LAPLACE TRANSFORM 418 A.3 THE LAPLACE TRANSFORM AND SAMPLING 418 A.4
SYSTEM MODELING WITH FREQUENCY RESPONSE 423 A.4.1 FREQUENCY RESPONSE OF
CONTINUOUS SYSTEMS 423 A.4.2 FREQUENCY RESPONSE OF SAMPLED SYSTEMS 428
A.5 RESPONSE IN THE TIME DOMAIN 431 A.6 FEEDBACK SYSTEMS 436 A.7
STEADY-STATE ERROR AND THE SYSTEM TYPE 440 A.8 STABILITY 441 A.9 ROOT
LOCUS 442 REFERENCES 445 APPENDIX B A REVIEW OF TRANSISTOR MODELS 447
B.L INTRODUCTION 447 B.2 THE BASICS OF CMOS TRANSISTORS 447 B.2.1 BASIC
DC BIASING CHARACTERISTICS 447 B.2.2 BASIC CMOS SQUARE LAW EQUATIONS 449
B.2.3 THE BODY EFFECT 450 B.2.4 HIGH-FREQUENCY EFFECTS 450 B.2.5 THERMAL
NOISE 451 B.2.6 SHOT NOISE 452 B.2.7 IIF NOISE 452 B.2.8 GATE NOISE 452
B.2.9 CMOS SMALL-SIGNAL MODEL, INCLUDING NOISE 453 B.3 BIPOLAR
TRANSISTORS 453 REFERENCES 457 ABOUT THE AUTHORS 459 INDEX 461
|
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| id | DE-604.BV021657056 |
| illustrated | Illustrated |
| indexdate | 2024-12-23T19:27:59Z |
| institution | BVB |
| isbn | 1580539823 |
| language | English |
| lccn | 2005044873 |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-014871608 |
| oclc_num | 62118429 |
| open_access_boolean | |
| owner | DE-29T DE-703 |
| owner_facet | DE-29T DE-703 |
| physical | xiii, 478 S. graph. Darst. 26 cm |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Artech House |
| record_format | marc |
| series2 | Artech House microwave library |
| spellingShingle | Rogers, John W. M. Plett, Calvin Dai, Foster Integrated circuit design for high-speed frequency synthesis Circuits intégrés à très grande vitesse - Conception et construction Very high speed integrated circuits Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd Hochfrequenz (DE-588)4160130-0 gnd Synthesizer Elektronik (DE-588)4184253-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| subject_GND | (DE-588)4179389-4 (DE-588)4160130-0 (DE-588)4184253-4 (DE-588)4027242-4 |
| title | Integrated circuit design for high-speed frequency synthesis |
| title_auth | Integrated circuit design for high-speed frequency synthesis |
| title_exact_search | Integrated circuit design for high-speed frequency synthesis |
| title_full | Integrated circuit design for high-speed frequency synthesis John Rogers, Calvin Plett, Foster Dai |
| title_fullStr | Integrated circuit design for high-speed frequency synthesis John Rogers, Calvin Plett, Foster Dai |
| title_full_unstemmed | Integrated circuit design for high-speed frequency synthesis John Rogers, Calvin Plett, Foster Dai |
| title_short | Integrated circuit design for high-speed frequency synthesis |
| title_sort | integrated circuit design for high speed frequency synthesis |
| topic | Circuits intégrés à très grande vitesse - Conception et construction Very high speed integrated circuits Design and construction Schaltungsentwurf (DE-588)4179389-4 gnd Hochfrequenz (DE-588)4160130-0 gnd Synthesizer Elektronik (DE-588)4184253-4 gnd Integrierte Schaltung (DE-588)4027242-4 gnd |
| topic_facet | Circuits intégrés à très grande vitesse - Conception et construction Very high speed integrated circuits Design and construction Schaltungsentwurf Hochfrequenz Synthesizer Elektronik Integrierte Schaltung |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=014871608&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT rogersjohnwm integratedcircuitdesignforhighspeedfrequencysynthesis AT plettcalvin integratedcircuitdesignforhighspeedfrequencysynthesis AT daifoster integratedcircuitdesignforhighspeedfrequencysynthesis |