Cross talk noise immune VLSI design using regular layout fabrics

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Khatri, Sunil P. (VerfasserIn), Brayton, Robert K. (VerfasserIn), Sangiovanni-Vincentelli, Alberto L. (VerfasserIn)
Format: Buch
Sprache:English
Veröffentlicht: Boston [u.a.] Kluwer Acad. Publ. 2001
Schlagworte:
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!

MARC

LEADER 00000nam a2200000 c 4500
001 BV013963971
003 DE-604
005 20020307
007 t|
008 011018s2001 xx d||| |||| 00||| eng d
020 |a 079237407X  |9 0-7923-7407-X 
035 |a (OCoLC)46835363 
035 |a (DE-599)BVBBV013963971 
040 |a DE-604  |b ger  |e rakwb 
041 0 |a eng 
049 |a DE-703 
050 0 |a TK7874.75 
082 0 |a 621.39/5  |2 21 
084 |a ZN 4950  |0 (DE-625)157424:  |2 rvk 
100 1 |a Khatri, Sunil P.  |e Verfasser  |4 aut 
245 1 0 |a Cross talk noise immune VLSI design using regular layout fabrics  |c Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli 
264 1 |a Boston [u.a.]  |b Kluwer Acad. Publ.  |c 2001 
300 |a XIX, 112 S.  |b graph. Darst. 
336 |b txt  |2 rdacontent 
337 |b n  |2 rdamedia 
338 |b nc  |2 rdacarrier 
650 4 |a Crosstalk  |x Prevention 
650 4 |a Integrated circuit layout 
650 4 |a Integrated circuits  |x Very large scale integration  |x Design and construction 
650 0 7 |a VLSI  |0 (DE-588)4117388-0  |2 gnd  |9 rswk-swf 
689 0 0 |a VLSI  |0 (DE-588)4117388-0  |D s 
689 0 |5 DE-604 
700 1 |a Brayton, Robert K.  |e Verfasser  |4 aut 
700 1 |a Sangiovanni-Vincentelli, Alberto L.  |e Verfasser  |4 aut 
943 1 |a oai:aleph.bib-bvb.de:BVB01-009557066 

Datensatz im Suchindex

_version_ 1819246542837514240
any_adam_object
author Khatri, Sunil P.
Brayton, Robert K.
Sangiovanni-Vincentelli, Alberto L.
author_facet Khatri, Sunil P.
Brayton, Robert K.
Sangiovanni-Vincentelli, Alberto L.
author_role aut
aut
aut
author_sort Khatri, Sunil P.
author_variant s p k sp spk
r k b rk rkb
a l s v als alsv
building Verbundindex
bvnumber BV013963971
callnumber-first T - Technology
callnumber-label TK7874
callnumber-raw TK7874.75
callnumber-search TK7874.75
callnumber-sort TK 47874.75
callnumber-subject TK - Electrical and Nuclear Engineering
classification_rvk ZN 4950
ctrlnum (OCoLC)46835363
(DE-599)BVBBV013963971
dewey-full 621.39/5
dewey-hundreds 600 - Technology (Applied sciences)
dewey-ones 621 - Applied physics
dewey-raw 621.39/5
dewey-search 621.39/5
dewey-sort 3621.39 15
dewey-tens 620 - Engineering and allied operations
discipline Elektrotechnik / Elektronik / Nachrichtentechnik
format Book
fullrecord <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01316nam a2200385 c 4500</leader><controlfield tag="001">BV013963971</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20020307 </controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">011018s2001 xx d||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">079237407X</subfield><subfield code="9">0-7923-7407-X</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)46835363</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV013963971</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-703</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7874.75</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">21</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Khatri, Sunil P.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Cross talk noise immune VLSI design using regular layout fabrics</subfield><subfield code="c">Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston [u.a.]</subfield><subfield code="b">Kluwer Acad. Publ.</subfield><subfield code="c">2001</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">XIX, 112 S.</subfield><subfield code="b">graph. Darst.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Crosstalk</subfield><subfield code="x">Prevention</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuit layout</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Brayton, Robert K.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Sangiovanni-Vincentelli, Alberto L.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-009557066</subfield></datafield></record></collection>
id DE-604.BV013963971
illustrated Illustrated
indexdate 2024-12-23T15:45:03Z
institution BVB
isbn 079237407X
language English
oai_aleph_id oai:aleph.bib-bvb.de:BVB01-009557066
oclc_num 46835363
open_access_boolean
owner DE-703
owner_facet DE-703
physical XIX, 112 S. graph. Darst.
publishDate 2001
publishDateSearch 2001
publishDateSort 2001
publisher Kluwer Acad. Publ.
record_format marc
spelling Khatri, Sunil P. Verfasser aut
Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli
Boston [u.a.] Kluwer Acad. Publ. 2001
XIX, 112 S. graph. Darst.
txt rdacontent
n rdamedia
nc rdacarrier
Crosstalk Prevention
Integrated circuit layout
Integrated circuits Very large scale integration Design and construction
VLSI (DE-588)4117388-0 gnd rswk-swf
VLSI (DE-588)4117388-0 s
DE-604
Brayton, Robert K. Verfasser aut
Sangiovanni-Vincentelli, Alberto L. Verfasser aut
spellingShingle Khatri, Sunil P.
Brayton, Robert K.
Sangiovanni-Vincentelli, Alberto L.
Cross talk noise immune VLSI design using regular layout fabrics
Crosstalk Prevention
Integrated circuit layout
Integrated circuits Very large scale integration Design and construction
VLSI (DE-588)4117388-0 gnd
subject_GND (DE-588)4117388-0
title Cross talk noise immune VLSI design using regular layout fabrics
title_auth Cross talk noise immune VLSI design using regular layout fabrics
title_exact_search Cross talk noise immune VLSI design using regular layout fabrics
title_full Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli
title_fullStr Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli
title_full_unstemmed Cross talk noise immune VLSI design using regular layout fabrics Sunil P. Khatri ; Robert K. Brayton ; Alberto L. Sangiovanni-Vincentelli
title_short Cross talk noise immune VLSI design using regular layout fabrics
title_sort cross talk noise immune vlsi design using regular layout fabrics
topic Crosstalk Prevention
Integrated circuit layout
Integrated circuits Very large scale integration Design and construction
VLSI (DE-588)4117388-0 gnd
topic_facet Crosstalk Prevention
Integrated circuit layout
Integrated circuits Very large scale integration Design and construction
VLSI
work_keys_str_mv AT khatrisunilp crosstalknoiseimmunevlsidesignusingregularlayoutfabrics
AT braytonrobertk crosstalknoiseimmunevlsidesignusingregularlayoutfabrics
AT sangiovannivincentellialbertol crosstalknoiseimmunevlsidesignusingregularlayoutfabrics