Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings
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|---|---|
| Sprache: | English |
| Veröffentlicht: |
Berlin [u.a.]
Springer
2000
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| Schriftenreihe: | Lecture notes in computer science
1918 |
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| 245 | 1 | 0 | |a Integrated circuit design |b power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings |c Dimitrios Soudris ... (ed.) |
| 264 | 1 | |a Berlin [u.a.] |b Springer |c 2000 | |
| 300 | |a XII, 338 S. |b Ill., graph. Darst. | ||
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| 490 | 1 | |a Lecture notes in computer science |v 1918 | |
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Datensatz im Suchindex
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|---|---|
| DE-BY-TUM_katkey | 1161885 |
| DE-BY-TUM_location | 01 |
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| _version_ | 1820878249656320000 |
| adam_text | TABLE OF CONTENTS
OPENING
CONSTRAINTS, HURDLES, AND OPPORTUNITIES
FOR A SUCCESSFUL EUROPEAN TAKE-UP ACTION
............................
1
R. VAN LEUKEN, R. NOUTA, A. DE GRAF (DELFT UNIVERSITY OF TECHNOLOGY,
THE NETHERLANDS)
RTL POWER MODELING
ARCHITECTURAL DESIGN SPACE EXPLORATION ACHIEVED
THROUGH INNOVATIVE RTL POWER ESTIMATION TECHNIQUES
..................
3
M. ANTON, M. CHINOSI, D. SIRTORI, R. ZAFALON (STMICROELECTRONICS,
ITALY)
POWER MODELS FOR SEMI-AUTONOMOUS RTL MACROS
......................
14
A. BOGLIOLO (UNIVERSITY OF FERRARA, ITALY)
E. MACII, V. MIHAILOVICI, M. PONCINO (POLYTECHNICAL UNIVERSITY OF
TORINO,
ITALY)
POWER MACRO-MODELLING FOR FIRM-MACRO
..............................
24
G. JOCHENS, L. KRUSE, E. SCHMIDT, A. STAMMERMANN, W. NEBEL
(OFFIS RESEARCH INSTITUTE, OLDENBURG, GERMANY)
RTL ESTIMATION OF STEERING LOGIC POWER
..............................
36
C. ANTON, P. CIVERA, I. COLONESCU, E. MACII, M. PONCINO
(POLYTECHNICAL UNIVERSITY OF TORINO, ITALY)
A. BOGLIOLO (UNIVERSITY OF FERRARA, ITALY)
POWER ESTIMATION AND OPTIMIZATION
REDUCING POWER CONSUMPTION THROUGH DYNAMIC FREQUENCY SCALING
FOR A CLASS OF DIGITAL RECEIVERS
......................................
47
N.D. ZERVAS, S. THEOHARIS, A.P. KAKAROUDAS, G. THEODORIDIS,
C.E. GOUTIS (UNIVERSITY OF PATRAS, GREECE)
D. SOUDRIS (DEMOCRITOS UNIVERSITY OF THRACE, GREECE)
FRAMEWORK FOR HIGH-LEVEL POWER ESTIMATION
OF SIGNAL PROCESSING ARCHITECTURES
....................................
56
A. FREIMANN (UNIVERSITY OF HANNOVER, GERMANY)
X TABLE OF CONTENTS
ADAPTIVE BUS ENCODING TECHIQUE FOR SWITCHING ACTIVITY REDUCED DATA
TRANSFER OVER WIDE SYSTEM BUSES
....................................
66
C. KRETZSCHMAR, R. SIEGMUND, D. M¨ULLER (CHEMNITZ UNIVERSITY
OF TECHNOLOGY, GERMANY)
ACCURATE POWER ESTIMATION OF LOGIC STRUCTURES
BASED ON TIMED BOOLEAN FUNCTIONS
..................................
76
G. THEODORIDIS, S. THEOHARIS, N.D. ZERVAS, C.E. GOUTIS
(UNIVERSITY OF PATRAS, GREECE)
SYSTEM-LEVEL DESIGN
A HOLISTIC APPROACH TO SYSTEM LEVEL ENERGY OPTIMIZATION
..............
88
M.J. IRWIN, M. KANDEMIR, N. VIJAYKRISHNAN, A. SIVASUBRAMANIAM
(THE PENNSYLVANIA STATE UNIVERSITY, USA)
EARLY POWER ESTIMATION FOR SYSTEM-ON-CHIP DESIGNS
...................
108
M. LAJOLO (NECC&CRESEARCH LABS, PRINCETON, USA)
L. LAVAGNO (UNIVERSITY OF UDINE, ITALY)
M. SONZA REORDA, M. VIOLANTE (POLYTECHNICAL UNIVERSITY OF TORINO,
ITALY)
DESIGN-SPACE EXPLORATION OF LOW POWER COARSE GRAINED RECONFIGURABLE
DATAPATH ARRAY ARCHITECTURES
.......................................
118
R. HARTENSTEIN, TH. HOFFMANN, U. NAGELDINGER (UNIVERSITY
OF KAISERSLAUTERN, GERMANY)
TRANSISTOR-LEVEL MODELING
INTERNAL POWER DISSIPATION MODELING AND MINIMIZATION
FOR SUBMICRONIC CMOS DESIGN
.......................................
129
P. MAURINE, M. REZZOUG, D. AUVERGNE (UNIVERSITY OF MONTPELLIER, FRANCE)
IMPACT OF VOLTAGE SCALING ON GLITCH POWER CONSUMPTION
................
139
H. ERIKSSON, P. LARSSON-EDEFORS (UNIVERSITY OF LINK¨OPING, SWEDEN)
DEGRADATION DELAY MODEL EXTENSION TO CMOS GATES
...................
149
J. JUAN-CHICO, M.J. BELLIDO, P. RUIZ-DE-CLAVIJO, A.J. ACOSTA,
M. VALENCIA (CENTRO NACIONAL DE MICROELECTR´ONICA, SEVILLA, SPAIN)
SECOND GENERATION DELAY MODEL FOR SUBMICRON CMOS PROCESS
..........
159
M. REZZOUG, P. MAURINE, D. AUVERGNE (UNIVERSITY OF MONTPELLIER, FRANCE)
ASYNCHRONOUS CIRCUIT DESIGN
SEMI-MODULAR LATCH CHAINS FOR ASYNCHRONOUS CIRCUIT DESIGN
............
168
N. STARODOUBTSEV, A. BYSTROV, A. YAKOVLEV (UNIVERSITY OF NEWCASTLE
UPON TYNE, UK)
TABLE OF CONTENTS XI
ASYNCHRONOUS FIRST-IN FIRST-OUT QUEUES
...............................
178
F. PESSOLANO (SOUTH BANK UNIVERSITY, LONDON, UK)
J.W.L. KESSELS (PHILIPS RESEARCH LABORATORIES, EINDHOVEN,
THE NETHERLANDS)
COMPARATIVE STUDY ON SELF-CHECKING CARRY-PROPAGATE ADDERS
IN TERMS OF AREA, POWER AND PERFORMANCE
.............................
187
A.P. KAKAROUDAS, K. PAPADOMANOLAKIS, V. KOKKINOS, C.E. GOUTIS
(UNIVERSITY OF PATRAS, GREECE)
VLSIIMPLEMENTATION OF A LOW- POWER HIGH-SPEED SELF-TIMED ADDER
.....
195
P. CORSONELLO, (UNIVERSITY OF REGGIO CALABRIA, ITALY)
S. PERRI, G. COCORULLO (UNIVERSITY OF CALABRIA, ITALY)
POWER EFFICIENT TECHNOLOGIES
LOW POWER DESIGN TECHNIQUES FOR CONTACTLESS CHIPCARDS
................
205
H. SEDLAK (INFINEON TECHNOLOGIES, MUNICH, GERMANY)
DYNAMIC MEMORY DESIGN FOR LOW DATA-RETENTION POWER
................
207
J. KIM, M.C. PAPAEFTHYMIOU (UNIVERSITY OF MICHIGAN, USA)
DOUBLE-LATCH CLOCKING SCHEME FOR LOW-POWER I.P. CORES
................
217
C. ARM, J.-M. MASGONTY, C. PIGUET (CSEM, SWITZERLAND)
DESIGN OF MULTIMEDIA PROCESSING APPLICATIONS
ARCHITECTURE, DESIGN, AND VERIFICATION OF AN 18 MILLION TRANSISTOR
DIGITAL
TELEVISION AND MEDIA PROCESSOR CHIP
.................................
225
S. DUTTA (PHILIPS SEMICONDUCTORS, SUNNYVALE, USA)
COST-EFFICIENT C-LEVEL DESIGN OF AN MPEG-4 VIDEO DECODER
.............
233
K. DENOLF, P. VOS, J. BORMANS, I. BOLSENS (IMEC, BELGIUM)
DATA-REUSE AND PARALLEL EMBEDDED ARCHITECTURES
FOR LOW-POWER, REAL-TIME MULTIMEDIA APPLICATIONS
....................
243
D. SOUDRIS, A. ARGYRIOU, M. DASYGENIS, K. TATAS, A. THANAILAKIS
(DEMOCRITUS UNIVERSITY OF THRACE, GREECE)
N.D. ZERVAS, C.E. GOUTIS (UNIVERSITY OF PATRAS, GREECE)
ADIABATICDESIGN AND ARITHMETICMODULES
DESIGN OF REVERSIBLE LOGIC CIRCUITS BY MEANS OF CONTROL GATES
..........
255
A. DE VOS, B. DESOETE (UNIVERSITY OF GENT, BELGIUM)
A. ADAMSKI, P. PIETRZAK, M. SIBINSKI, T. WIDERSKI (POLIYTECHNICAL
UNIVERSITY OF ;
L´ODZ, POLAND)
XII TABLE OF CONTENTS
MODELING OF POWER CONSUMPTION OF ADIABATIC GATES VERSUS FAN IN
AND COMPARISON WITH CONVENTIONAL GATES
.............................
265
M. ALIOTO, G. PALUMBO (UNIVERSITY OF CATANIA, ITALY)
AN ADIABATIC MULTIPLIER
............................................
276
C. SAAS, A. SCHLAFFER, J.A. NOSSEK (TECHNICAL UNIVERSITY OF MUNICH,
GERMANY)
LOGARITHMIC NUMBER SYSTEM FOR LOW-POWER ARITHMETIC
.................
285
V. PALIOURAS, T. STOURAITIS (UNIVERSITY OF PATRAS, GREECE)
ANALOG-DIGITAL CIRCUITS MODELING
AN APPLICATION OF SELF-TIMED CIRCUITS TO THE REDUCTION OF SWITCHING
NOISE
IN ANALOG-DIGITAL CIRCUITS
...........................................
295
R. JIM´ENEZ, A.J. ACOSTA, E.J. PERAL´*AS, A. RUEDA
(CENTRO NACIONAL DE MICROELECTR´ONICA, SEVILLA, SPAIN)
PARCOURS * SUBSTRATE CROSSTALK ANALYSIS
FOR COMPLEX MIXED-SIGNAL-CIRCUITS
...................................
306
A. HERMANN, E. BARKE (UNIVERSITY OF HANNOVER, GERMANY)
M. SILVANT (SIMPLEX SOLUTIONS, VOIRON, FRANCE)
J. SCHL¨OFFEL (PHILIPS SEMICONDUCTORS, HAMBURG, GERMANY)
INFLUENCE OF CLOCKING STRATEGIES ON THE DESIGN OF LOW SWITCHING-NOISE
DIGITAL AND MIXED-SIGNAL VLSICIRCUITS
...............................
316
A.J. ACOSTA, R. JIM´ENEZ, J. JUAN, M.J. BELLIDO, M. VALENCIA
(CENTRO NACIONAL DE MICROELECTR´ONICA / UNIVERSITY OF SEVILLA, SPAIN)
COMPUTER AIDED GENERATION OF ANALYTIC MODELS
FOR NONLINEAR FUNCTION BLOCKS
.......................................
327
T. WICHMANN (UNIVERSITY OF KAISERSLAUTERN, GERMANY)
M. THOLE (INFINEON TECHNOLOGIES, MUNICH, GERMANY)
AUTHOR INDEX
.................................................
337
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| illustrated | Illustrated |
| indexdate | 2024-12-23T15:25:42Z |
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| physical | XII, 338 S. Ill., graph. Darst. |
| publishDate | 2000 |
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| publisher | Springer |
| record_format | marc |
| series | Lecture notes in computer science |
| series2 | Lecture notes in computer science |
| spellingShingle | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings Lecture notes in computer science Entwurfsautomation - Kongress - Göttingen <2000> Entwurfsautomation (DE-588)4312536-0 gnd |
| subject_GND | (DE-588)4312536-0 (DE-588)1071861417 |
| title | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings |
| title_auth | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings |
| title_exact_search | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings |
| title_full | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings Dimitrios Soudris ... (ed.) |
| title_fullStr | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings Dimitrios Soudris ... (ed.) |
| title_full_unstemmed | Integrated circuit design power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings Dimitrios Soudris ... (ed.) |
| title_short | Integrated circuit design |
| title_sort | integrated circuit design power and timing modeling optimization and simulation 10th international workshop patmos 2000 gottingen germany september 13 15 2000 proceedings |
| title_sub | power and timing modeling, optimization and simulation ; 10th international workshop, PATMOS 2000, Göttingen, Germany, September 13 - 15, 2000 ; proceedings |
| topic | Entwurfsautomation - Kongress - Göttingen <2000> Entwurfsautomation (DE-588)4312536-0 gnd |
| topic_facet | Entwurfsautomation - Kongress - Göttingen <2000> Entwurfsautomation Konferenzschrift 2000 Göttingen |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=009087738&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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