Proceedings Västerås, Sweden, August 25 - 27, 1998 1 Workshop A. Digital Systems Design. Workshop B. Dependable Computing Systems
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Los Alamitos, Calif. [u.a.]
IEEE Computer Soc.
1998
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| 111 | 2 | |a EUROMICRO |n 24 |d 1998 |c Västerås |j Verfasser |0 (DE-588)5340811-1 |4 aut | |
| 245 | 1 | 0 | |a Proceedings |b Västerås, Sweden, August 25 - 27, 1998 |n 1 |p Workshop A. Digital Systems Design. Workshop B. Dependable Computing Systems |c 24th EUROMICRO Conference |
| 264 | 1 | |a Los Alamitos, Calif. [u.a.] |b IEEE Computer Soc. |c 1998 | |
| 300 | |a LIV, 483 S. |b Ill., graph. Darst. | ||
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| 655 | 7 | |0 (DE-588)1071861417 |a Konferenzschrift |2 gnd-content | |
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IMAGE 1
JL J\.\J VC Q T2IIJXJLN VJ O*
CRO CONFERENCE
VASTERAS, SWEDEN
AUGUST 25-27,1998
SPONSORED BY
SUN. MICROSYSTEMS
THENETWORK ISTHECOMPUTET-
SENATOR ABK NETWORK PARTNER
ERICSSON
»»» GENERATION #%WW ,%L
ABB INDUSTRIAL SYSTEMS HALARDALENSH6GSKOLA
IEEE
COMPUTER SOCIETY LOS ALAMITOS, CALIFORNIA
WASHINGTON * BRUSSELS * TOKYO
IMAGE 2
X ADIE 01 VE^ONIVLLLS
EUROMICRO'98
MESSAGE FROM THE GENERAL PROGRAM CHAIR XIX
MESSAGE FROM THE ORGANIZING CHAIR XX
VOLUME I
WORKSHOP A. DIGITAL SYSTEMS DESIGN
MESSAGE FROM THE WORKSHOP A CHAIR XXI
K. KUCHCINSM
WORKSHOP A PROGRAM COMMITTEE XXII
WORKSHOP A REVIEWERS XXII
KEYNOTE SPEECH KEYNOTE B. ERICSON
SESSION A.1: COMBINATIONAL LOGIC DESIGN CHAIR: M. PERKOWSKI
SOLVING SYNTHESIS PROBLEMS WITH GENETIC ALGORITHMS 1
L. JOZWIAK, N. EDERVEEN, A. POSTULA
EFFICIENT LOGIC SYNTHESIS FOR FPGAS WITH FUNCTIONAL DECOMPOSITION BASED
ON INFORMATION RELATIONSHIP MEASURES 8
M. RAWSKI, L. JOZWIAK, T. LUBA, A. CHOJNACKI
AN EFFICIENT APPROACH TO DECOMPOSITION OFMULTI-OUTPUT BOOLEAN FUNCTIONS
WITH LARGE SETS OF BOUND VARIABLES 16
M. BURNS, M, PERKOWSKI, 1. JDZWIAK
A RECONFIGURABLE PRINTED CHARACTER RECOGNITION SYSTEM USING A LOGIC
SYNTHESIS TOOL 24 H. SELVARAJ, M. VENKATESAN
SESSIONA.2: POSTER PRESENTATIONS CHAIR: K. KUCHCINSKI
DESIGN CORRECTNESS OF DIGITAL SYSTEMS 30
C. HUIJS
PERFORMING HIGH-LEVEL SYNTHESIS VIA PROGRAM TRANSFORMATIONS WITHIN A
THEOREM PROVER 34 C. BLUMENROHR, D. EISENBIEGLER
V
IMAGE 3
SPECIFICATION OF EXCEPTION HANDLING IN GRAMMAR-BASED HARDWARE SYNTHESIS
38
J. OBERG, A. KUMAR, A. HEMANI
RULE BASE DRIVEN CONVERSION OF AN OBJECT ORIENTED DESIGN DATA STRUCTURE
INTO STANDARD HARDWARE DESCRIPTION LANGUAGES 42
A. VERSCHUEREN
VERIFICATION OFEMBEDDEDREAL-TIME SYSTEMS USING HARDWARE/SOFTWARE
CO-SIMULATION 46 M. EL SHOBAKI
EFFICIENT COMBINATIONAL LOOPS HANDLING FOR CYCLE PRECISE SIMULATION OF
SYSTEM ON A CHIP 51 D. HOMMAIS, F. PETROT
GRAMMAR BASED MODELLING AND SYNTHESIS OFDEVICE DRIVERS ANDBUS INTERFACES
55
M. 0 'NILS, J. OBERG, A. JANTSCH
OPTIMAL SYSTEM-LEVEL SYNTHESIS OFDIGITAL SYSTEMS FOR REAL-TIME
APPLICATIONS 59
A. BENDER
A UNIFIED COMPONENT MODELING APPROACH FOR PERFORMANCE ESTIMATION IN
HARDWARE/SOFTWARE CODESIGN 65
J. GRADE, J. MADSEN
A FPGA IMPLEMENTATION OF A VIDEO RATE MULTI-TARGET TRACKING SYSTEM 70
J. ARANDA, C. CLIMENT, A. GRAU
SESSION A.3: HIGH-LEVEL SYNTHESIS CHAIR: P. ELES
AN APPROACH TO HIGH-LEVEL SYNTHESIS USING CONSTRAINT LOGIC PROGRAMMING
74
K. KUCHCINSKI
OPERATION BINDING AND SCHEDULING FOR LOW POWER USING CONSTRAINT LOGIC
PROGRAMMING 83 F. GRUIAN, K. KUCHCINSKI
EXPLOITING THE USE OF VHDL SPECIFICATIONS IN THE AGENDA
HIGH-LEVEL SYNTHESIS ENVIRONMENT 91
G. ECONOMAKOS, G. PAPAKONSTANTINOU
REGISTER ALLOCATION WITH SIMULTANEOUS BIST INTRUSION 99
K. OLCOZ, J. TIRADO
AN IMPROVED REGISTER-TRANSFERLEVEL FUNCTIONAL PARTITIONINGAPPROACH FOR
TESTABILITY 107 T. YANG, Z. PENG
SESSION A.4: CUSTOM COMPUTING MACHINES CHAIR: L. J6ZWIAK
AUTOMATED SYNTHESISOF INTERLEAVED MEMORY SYSTEMS FOR CUSTOM COMPUTING
MACHINES 115 A. POSTULA, S, CHEN, L. JOZWIAK, D. ABRAMSON
IMAGE CONVOLUTION ONFPGAS: THE IMPLEMENTATIONOF A MULTI-FPGA FIFO
STRUCTURE 123 A. BENEDETTI, A, PRATI, N. SCARABOTTOLO
VI
IMAGE 4
PIPELINE ARCHITECTURE OF SPECIALIZED RECONFIGURABLE PROCESSORS IN FPGA
STRUCTURES FOR A REAL-TIME IMAGE PRE-PROCESSING K. WIATR 131
ARITHMETIC IMAGE CODING/DECODING ARCHITECTURE BASED ON A CACHEMEMORY 139
R. OSORIO, M. BOO, J. BRUGUERA
SESSION A.5: SYSTEM LEVEL DESIGN CHAIR: K. KUCHCINSKI
HARDWARE ARCHITECTURE MODELLING USING AN OBJECT-ORIENTED METHOD 147
F. MALLET, F. BOERI, J. DUBOC
SYSTEM LEVEL MODELLING FOR HARDWARE/SOFTWARE SYSTEMS 154
J. VOETEN, P. VAN DERPUITEN,
M. GEILEN, M. STEVENS
HARDWARE-SOFTWARE RUN-TIME SYSTEMS AND ROBOTICS: A CASE STUDY 162
V. MOONEY III, D. RUSPINI,
O.KHATIB, G. DE MICHELI
PROCESS SCHEDULING FOR PERFORMANCE ESTIMATION AND SYNTHESIS OF
HARDWARE/SOFTWARE SYSTEMS 168
P. ELES, K. KUCHCINSKI, Z. PENG, A. DOBOLI, P. POP
SESSION A.6: POSTER PRESENTATIONS CHAIR: L. JOZWIAK
MINIMIZATION OF ALGORITHMIC STATE MACHINES 176
S. BARANOV
HOW FAULTS CAN BE SIMULATED IN SELF-TESTABLE VLSI DIGITAL CIRCUITS 180
D. BOJANOWICZ
EXPERIMENTAL EVALUATION OF PSEUDORANDOM TEST EFFECTIVENESS 184
J. SOSNOWSKI
ENTROPY-BASED DESIGN OFLOW POWER FSMS 188
L. KASHIROVA, O. TVERETINA
RSR: A NEW RECTILINEAR STEINER MINIMUM TREE APPROXIMATION FOR FPGA
PLACEMENT AND GLOBAL ROUTING 192
J. DE VICENTE, J. LANCHARES, R, HERMIDA
MODIFIED APPROACH TO AUTOMATA STATE ENCODING FOR LUT FPGA IMPLEMENTATION
196
I. LEMBERSKI
DESIGN OFVIRTUAL DIGITAL CONTROLLERS BASED ON DYNAMICALLY RECONFIGURABLE
FPGAS 200 V. SKLYAROV, N. LAU, R. MONTEIRO, A. OLIVEIRA, A. MELO ANDK.
KONDRATJUK
THE IMPACT OFAREA OPTIMIZATION FOR THE POWER CONSUMPTION OF CONTROLLERS
204
H. DAHMEN, U. GLDSER
VII
IMAGE 5
EXTENDING A MONOPROCESSOR REAL-TIME SYSTEM IN A
MULTIPROCESSING ENVIRONMENT, DSP-BASED 208
S. AIELLO ET AL.
A USEFUL MICROPIPELINE ARCHITECTURE TO IMPLEMENT DSP ALGORITHMS 212
C. CHOY, T. PANG, J. POVAZANEC, C. CHAN
SESSION A.7: APPLICATIONS CHAIR: L. LINDH
CONTROL SYSTEM FOR A LOW ENERGY PARTICLE DETECTION 216
5". SANCHEZ, D. MEZIAT, M. CARBAJO,
J. MEDINA, E, BRONCHALO, J. RODRIGUEZ-PACHECO, L. DEL PERAL
DELFT-JAVA LINK TRANSLATION BUFFER 221
/. GLOSSNER, S. VASSILIADIS
SESSION A.8: REAL-TIME EMBEDDED SYSTEMS CHAIR: L. LINDH
VERIFICATION OFREALTIME CONTROLLERS AGAINST TIMING DIAGRAM
SPECIFICATIONS USING CONSTRAINT LOGIC PROGRAMMING 229
E. CERNY, F. JIN
RATE ASSIGNMENT FOR EMBEDDED REACTIVE REAL-TIME SYSTEMS 237
Y SHIN, K. CHOI
HARDWARE TO SOFTWARE MIGRATION WITH REAL-TIME THREAD INTEGRATION 243
A. DEAN, J. SHEN
SESSION A.9: SEQUENTIAL LOGIC SYNTHESIS CHAIR: S. BARANOV
DESIGN OF SELF-SYNCHRONIZED COMPONENT FSMS FOR SELF-TIMED SYSTEMS 253
L. NGUEN, M. PERKOWSKI, L. JOZWIAK
MULTI-CRITERIAL STATE ASSIGNMENT FOR LOW POWER FSM DESIGN 261
M. KOEGST, G, FRANKE, S. RULKE, K. FESKE
A NEW APPROACH TO AND/OR/EXOR FACTORIZATION FOR REGULAR ARRAYS 269
N. SONG, M. PERKOWSKI
SESSIONA.10: PROCESSOR AND PARALLEL ARCHITECTURES CHAIRPERSON: F. TIRADO
ON THE DESIGN COMPLEXITY OFTHE ISSUE LOGIC OF SUPERSCALAR MACHINES 277
S. COTOFANA, S. VASSILIADIS
DATA DEPENDENCE SPECULATION USING DATA ADDRESS PREDICTION AND ITS
ENHANCEMENT WITH INSTRUCTION REISSUE 285
T. SATO
THE LATENCY HIDING EFFECTIVENESS OF DECOUPLED ACCESS/EXECUTE PROCESSORS
293
J. PARCERISA, A. GONZALEZ
* * *
VM
IMAGE 6
REVOLVER: A HIGH-PERFORMANCE MIMD ARCHITECTURE FOR COLLISION FREE
COMPUTING 301
J. OBERG, P. ELLERVEE
SESSION A.LL: POSTER PRESENTATIONS CHAIRPERSON: A. NUNEZ
A GROUPING PARTITIONING TECHNIQUE WITH AUTOMATIC CRITERION SELECTION FOR
THE CODESIGN PROCESS 309
J. MAESTRO, D. MOZOS, J. SEPTIEN
HIERARCHICAL CONDITIONAL DEPENDENCY GRAPHS FOR CONDITIONAL RESOURCE
SHARING 313
A. KOUNTOURIS, C. WOLINSKI
FORMAL EXTRACTION OF MEMORIZING ELEMENTS FOR SEQUENTIAL VHDL SYNTHESIS
317
L. JACOMME, F. PETROL, R. BAWA
DATA SPECULATIVE MULTITHREADED ARCHITECTURE 321
P. MARCUELLO, A. GONZALEZ
THE IMPACT OFA REALISTIC CACHE STRUCTURE ON A STATICALLY SCHEDULED
ARCHITECTURE 325
D. TATE, G. STEVEN, P. FINDLAY
HOW TO HALFTHE LATENCY OF IEEE COMPLIANT FLOATING-POINT MULTIPLICATION
329
P. SEIDEL
IMPACT OF REDUCING MISS WRITE LATENCIES IN MULTIPROCESSORS WITH TWO
LEVEL CACHE 333 J. SAHUQUILLO, A, PONT
EFFICIENT HIGH-SPEED CMOS DESIGN BY LAYOUT BASED SCHEMATIC METHOD 337
F. MU, C. SVENSSON
A MINIATURE SERIAL-DATA SIMD ARCHITECTURE 341
P, LARSSON-EDEFORS
CACHE PROBABILISTICMODELING FOR BASIC SPARSE ALGEBRA KERNELS INVOLVING
MATRICES WITH ANON UNIFORM DISTRIBUTION 345
R. DOALLO, B. FRAGUELA, E. ZAPATA
SESSION A.12: HIGH-LEVEL SYNTHESIS N CHAIR: M. FERNANDEZ
ESTIMATION AND CONSIDERATION OFINTERCONNECTIONDELAYS DURING HIGH-LEVEL
SYNTHESIS 349 /. HALLBERG, Z. PENG
DESIGN OF CONTROL DOMINATED HARDWARE BASED ON FORMALMETHODS 357
W. GRASS, S. LENK, C. SONTHEIM
A METHOD FOR MAPPING DSP ALGORITHMS INTO APPLICATION SPECIFIC STRUCTURES
365
A. SERGYIENKO, J. KANEVSKI, 0. MASLENNIKOV, R. WYRZYKOWSKI
IX
IMAGE 7
WORKSHOP B. DEPENDABLE COMPUTING SYSTEMS
MESSAGEFROM THE WORKSHOP B CHAIR XXIII
A. TYRRELL
WORKSHOP B PROGRAM COMMITTEE XXIV
WORKSHOP B REVIEWERS XXIV
KEYNOTE SPEECH DESIGN, TESTING AND EVALUATION TECHNIQUES FOR SOFTWARE
RELIABILITY ENGINEERING XXXIX
M. LYU
SESSION B.L: MASKING TECHNIQUES CHAIR: L. SILVA
SIMULATION OF A COMPONENT-ORIENTED VOTER LIBRARY FOR DEPENDABLE CONTROL
APPLICATIONS 372 G. LATIF-SHABGAHI, J. BASS, S. BENNETT
THE EFTOS VOTING FARM: A SOFTWARE TOOL FOR FAULTMASKING IN MESSAGE
PASSING PARALLEL ENVIRONMENTS 379
V. DE FLORIO, G. DECONINCK, R. LAUWEREINS
GENERATING MULTIPLE DIVERSE SOFTWARE VERSIONS WITH GENETIC PROGRAMMING
387
R. FELDT
SESSION B.2: RECOVERY TECHNIQUES CHAIR: A. TYRRELL
AN EXPERIMENTAL STUDY ABOUT DISKLESS CHECKPOINTING 395
L. SILVA, J. SILVA
DISTRIBUTED CHECKPOINT ALGORITHMS TO AVOID ROLL-BACK PROPAGATION 403
F. ZAMBONELLI
DYNAMIC ACCEPTANCE TESTS FORCOMPLEX CONTROLLERS 411
R. STROPH, T. CLARKE
SESSION B.3: FAULT INJECTION, DIAGNOSIS AND DEBUGGING CHAIR: J. BASS
FAULT INJECTION INTO VHDL MODELS: ANALYSIS OF THE ERROR SYNDROME OF A
MICROCOMPUTER SYSTEM 418
D. GIL, J. BARAZA, J. BUSQUETS, P. GIL
CONTROL-FLOW SYSTEMS DIAGNOSIS: AN EVOLUTIVE METHOD M. KHALIL, Y. LE
TRAON, C. ROBACH
ON-THE-FLY MODEL CHECKING OF PROGRAMRUNS FOR AUTOMATED DEBUGGING 426
M. FREY, B. SCHLINGLOFF
X
IMAGE 8
SESSION B.4: DEVELOPMENT APPROACHES CHAIR: K. GROSSPIETSCH
ON THE EFFECTIVENESS OFSLICING HIERARCHICAL STATE MACHINES: A CASE STUDY
435
M. HEIMDAHL, J. THOMPSON, M. WHALEN
ENGINEERING SAFE, REAL-TIME DISTRIBUTED CONTROL SYSTEMS 445
P. CROLL, C. RUDRAM, C. CHAMBERS, N. UCHIHIRA
TOWARDS STANDARD-BASED SPECIFICATION AND DESIGN OFEMBEDDED REAL-TIME
SYSTEMS 453 R. GUMZEJ, M. COLNARIC, D. VERBER, W. HALANG
SESSION B.5: FAULT TREATMENT CHAIR: W. HOHL
A 32-BIT RISC PROCESSOR WITH CONCURRENT ERROR DETECTION 461
A. MAAMAR, G. RUSSELL
AN EXPERIMENTAL INVESTIGATION OFMESSAGE LATENCIES IN THE TOTEM PROTOCOL
IN THE PRESENCE OFFAULTS 468
K. HOLGER, M. WERNER, L. KUTTNER
APPROACHES FOR SCHEDULING OF TRIGGERED TRANSACTIONS IN REAL-TIME ACTIVE
DATABASE SYSTEMS 476
K. LAM, T. LEE
VOLUME II
WORKSHOP C. MULTIMEDIA AND TELECOMMUNICATIONS
MESSAGE FROM THE WORKSHOP C CHAIR XXV
F. PATRICELLI
WORKSHOP C PROGRAM COMMITTEE XXVI
WORKSHOP C REVIEWERS XXVI
KEYNOTE SPEECH TINA: SERVICE ARCHITECTURE IN MULTIMEDIA COMMUNICATIONS
D. GUHA
SESSION C.L:FORMAL SPECIFICATIONS CHAIR: S. DORMIDO
MULTI-VIEW SPECIFICATION OF CSCW APPLICATIONS 484
M. FREY-PUDKO, M. FREY
MODELING AND QUERYING VIDEO DATABASES 492
C. DECLEIR, M. HACID, J. KOULOUMDJIAN
XI |
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| spelling | EUROMICRO 24 1998 Västerås Verfasser (DE-588)5340811-1 aut Proceedings Västerås, Sweden, August 25 - 27, 1998 1 Workshop A. Digital Systems Design. Workshop B. Dependable Computing Systems 24th EUROMICRO Conference Los Alamitos, Calif. [u.a.] IEEE Computer Soc. 1998 LIV, 483 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier (DE-588)1071861417 Konferenzschrift gnd-content (DE-604)BV012625601 1 GBV Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=008576656&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Proceedings Västerås, Sweden, August 25 - 27, 1998 |
| subject_GND | (DE-588)1071861417 |
| title | Proceedings Västerås, Sweden, August 25 - 27, 1998 |
| title_auth | Proceedings Västerås, Sweden, August 25 - 27, 1998 |
| title_exact_search | Proceedings Västerås, Sweden, August 25 - 27, 1998 |
| title_full | Proceedings Västerås, Sweden, August 25 - 27, 1998 1 Workshop A. Digital Systems Design. Workshop B. Dependable Computing Systems 24th EUROMICRO Conference |
| title_fullStr | Proceedings Västerås, Sweden, August 25 - 27, 1998 1 Workshop A. Digital Systems Design. Workshop B. Dependable Computing Systems 24th EUROMICRO Conference |
| title_full_unstemmed | Proceedings Västerås, Sweden, August 25 - 27, 1998 1 Workshop A. Digital Systems Design. Workshop B. Dependable Computing Systems 24th EUROMICRO Conference |
| title_short | Proceedings |
| title_sort | proceedings vasteras sweden august 25 27 1998 workshop a digital systems design workshop b dependable computing systems |
| title_sub | Västerås, Sweden, August 25 - 27, 1998 |
| topic_facet | Konferenzschrift |
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