Parallel logic-level simulation system on a distributed memory machine
Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assig...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1991
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum
1030 |
| Schlagworte: | |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
MARC
| LEADER | 00000nam a2200000 cb4500 | ||
|---|---|---|---|
| 001 | BV010970708 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t| | ||
| 008 | 960925s1991 xx |||| 00||| engod | ||
| 035 | |a (OCoLC)25797516 | ||
| 035 | |a (DE-599)BVBBV010970708 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G | ||
| 100 | 1 | |a Matsumoto, Yukinori |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Parallel logic-level simulation system on a distributed memory machine |c by Y. Matsumoto & K. Taki |
| 264 | 1 | |a Tokyo, Japan |c 1991 | |
| 300 | |a 7 S. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |v 1030 | |
| 520 | 3 | |a Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assigned to gates in the circuits. This paper proposes a new partitioning strategy of circuit data that is efficient for Virtual Time and also reports the measurement results of the simulator. In our experiment, a sequential circuit consisting of over 10,000 gates was simulated. Using 64 processors, the system indicated about 47k events/sec as its performance, and also indicated about 47 times speedup | |
| 520 | 3 | |a This paper, using these results, denotes that Virtual Time is an efficient local synchronization mechanism and the new partitioning strategy proposed here can be a practical strategy. | |
| 650 | 4 | |a Integrated circuits |x Design and construction | |
| 700 | 1 | |a Taki, Kazuo |e Verfasser |4 aut | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |v 1030 |w (DE-604)BV010943497 |9 1030 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007340373 | |
Datensatz im Suchindex
| DE-BY-TUM_call_number | 0111 2001 B 6122 |
|---|---|
| DE-BY-TUM_katkey | 767335 |
| DE-BY-TUM_location | 01 |
| DE-BY-TUM_media_number | 040010302924 |
| _version_ | 1820891765905817601 |
| any_adam_object | |
| author | Matsumoto, Yukinori Taki, Kazuo |
| author_facet | Matsumoto, Yukinori Taki, Kazuo |
| author_role | aut aut |
| author_sort | Matsumoto, Yukinori |
| author_variant | y m ym k t kt |
| building | Verbundindex |
| bvnumber | BV010970708 |
| ctrlnum | (OCoLC)25797516 (DE-599)BVBBV010970708 |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01931nam a2200313 cb4500</leader><controlfield tag="001">BV010970708</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">960925s1991 xx |||| 00||| engod</controlfield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)25797516</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV010970708</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Matsumoto, Yukinori</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Parallel logic-level simulation system on a distributed memory machine</subfield><subfield code="c">by Y. Matsumoto & K. Taki</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Tokyo, Japan</subfield><subfield code="c">1991</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">7 S.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="1" ind2=" "><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum</subfield><subfield code="v">1030</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">Abstract: "We have just constructed a parallel logic-level simulation system based on Virtual Time. It was implemented on the Multi- PSI, the experimental parallel inference machine developed at ICOT. Our system simulates sequential circuits of practical size. Different delay times can be assigned to gates in the circuits. This paper proposes a new partitioning strategy of circuit data that is efficient for Virtual Time and also reports the measurement results of the simulator. In our experiment, a sequential circuit consisting of over 10,000 gates was simulated. Using 64 processors, the system indicated about 47k events/sec as its performance, and also indicated about 47 times speedup</subfield></datafield><datafield tag="520" ind1="3" ind2=" "><subfield code="a">This paper, using these results, denotes that Virtual Time is an efficient local synchronization mechanism and the new partitioning strategy proposed here can be a practical strategy.</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Taki, Kazuo</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="830" ind1=" " ind2="0"><subfield code="a">Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum</subfield><subfield code="v">1030</subfield><subfield code="w">(DE-604)BV010943497</subfield><subfield code="9">1030</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-007340373</subfield></datafield></record></collection> |
| id | DE-604.BV010970708 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-23T14:18:16Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007340373 |
| oclc_num | 25797516 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 7 S. |
| publishDate | 1991 |
| publishDateSearch | 1991 |
| publishDateSort | 1991 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum |
| spellingShingle | Matsumoto, Yukinori Taki, Kazuo Parallel logic-level simulation system on a distributed memory machine Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical memorandum Integrated circuits Design and construction |
| title | Parallel logic-level simulation system on a distributed memory machine |
| title_auth | Parallel logic-level simulation system on a distributed memory machine |
| title_exact_search | Parallel logic-level simulation system on a distributed memory machine |
| title_full | Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki |
| title_fullStr | Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki |
| title_full_unstemmed | Parallel logic-level simulation system on a distributed memory machine by Y. Matsumoto & K. Taki |
| title_short | Parallel logic-level simulation system on a distributed memory machine |
| title_sort | parallel logic level simulation system on a distributed memory machine |
| topic | Integrated circuits Design and construction |
| topic_facet | Integrated circuits Design and construction |
| volume_link | (DE-604)BV010943497 |
| work_keys_str_mv | AT matsumotoyukinori parallellogiclevelsimulationsystemonadistributedmemorymachine AT takikazuo parallellogiclevelsimulationsystemonadistributedmemorymachine |