PIM k, a parallel inference machine with a cache hierarchy
Abstract: "This paper presents the features of PIM/k, one of the Parallel Inference Machines being developed under the Japan's Fifth Generation Computer Project. One of the primary goals of the project is to realize a fast inference machine by means of parallel processing. Towards this goa...
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| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Tokyo, Japan
1992
|
| Schriftenreihe: | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report
768 |
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| 245 | 1 | 0 | |a PIM k, a parallel inference machine with a cache hierarchy |c by H. Sakai ... |
| 264 | 1 | |a Tokyo, Japan |c 1992 | |
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| 490 | 1 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 768 | |
| 520 | 3 | |a Abstract: "This paper presents the features of PIM/k, one of the Parallel Inference Machines being developed under the Japan's Fifth Generation Computer Project. One of the primary goals of the project is to realize a fast inference machine by means of parallel processing. Towards this goal, PIM/k employs a cache hierarchy to reduce the memory access latency, while the other PIMs employ inter-cluster networks to obtain high band-width of the whole systems. This paper describes the design considerations of a hierarchical cache consistency protocol with an efficient replacement algorithm. The KL1 system software which was initially designed for the inter-cluster networks of the other PIMs should be tuned for the cache hierarchy | |
| 520 | 3 | |a This paper shows that the cache hierarchy is advantageous from the software points of view and that stop-and-copy GC employed by the PIMs requires adapting in order to avoid an efficiency problem. Though PIM/k is still under development, this paper also reports a KL1 program evaluation on the actual machine with 4 processing elements (PEs). | |
| 650 | 4 | |a Fifth generation computers | |
| 650 | 4 | |a KL1 (Computer program language) | |
| 650 | 4 | |a Logic programming | |
| 650 | 4 | |a Parallel processing (Electronic computers) | |
| 700 | 1 | |a Sakai, Hiroshi |e Sonstige |4 oth | |
| 830 | 0 | |a Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |v 768 |w (DE-604)BV010923438 |9 768 | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-007328863 | |
Datensatz im Suchindex
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| id | DE-604.BV010956766 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-23T14:18:00Z |
| institution | BVB |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-007328863 |
| oclc_num | 27424365 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM |
| owner_facet | DE-91G DE-BY-TUM |
| physical | 14 S. |
| publishDate | 1992 |
| publishDateSearch | 1992 |
| publishDateSort | 1992 |
| record_format | marc |
| series | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| series2 | Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report |
| spellingShingle | PIM k, a parallel inference machine with a cache hierarchy Shin-Sedai-Konpyūta-Gijutsu-Kaihatsu-Kikō <Tōkyō>: ICOT technical report Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) |
| title | PIM k, a parallel inference machine with a cache hierarchy |
| title_auth | PIM k, a parallel inference machine with a cache hierarchy |
| title_exact_search | PIM k, a parallel inference machine with a cache hierarchy |
| title_full | PIM k, a parallel inference machine with a cache hierarchy by H. Sakai ... |
| title_fullStr | PIM k, a parallel inference machine with a cache hierarchy by H. Sakai ... |
| title_full_unstemmed | PIM k, a parallel inference machine with a cache hierarchy by H. Sakai ... |
| title_short | PIM k, a parallel inference machine with a cache hierarchy |
| title_sort | pim k a parallel inference machine with a cache hierarchy |
| topic | Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) |
| topic_facet | Fifth generation computers KL1 (Computer program language) Logic programming Parallel processing (Electronic computers) |
| volume_link | (DE-604)BV010923438 |
| work_keys_str_mv | AT sakaihiroshi pimkaparallelinferencemachinewithacachehierarchy |