Circuit analysis, simulation and design
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| Format: | Buch |
|---|---|
| Sprache: | Undetermined |
| Veröffentlicht: |
Amsterdam u.a.
North-Holland
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| Schriftenreihe: | Advances in CAD for VLSI
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MARC
| LEADER | 00000nam a2200000 ca4500 | ||
|---|---|---|---|
| 001 | BV009500750 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | t| | ||
| 008 | 940401nuuuuuuuuxx |||| 00||| und d | ||
| 020 | |a 0444878939 |9 0-444-87893-9 | ||
| 020 | |a 0444878904 |9 0-444-87890-4 | ||
| 020 | |a 0444878890 |9 0-444-87889-0 | ||
| 035 | |a (DE-599)BVBBV009500750 | ||
| 040 | |a DE-604 |b ger |e rakddb | ||
| 041 | |a und | ||
| 084 | |a ST 190 |0 (DE-625)143607: |2 rvk | ||
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 245 | 1 | 0 | |a Circuit analysis, simulation and design |c ed. by A. E. Ruehli |
| 264 | 1 | |a Amsterdam u.a. |b North-Holland | |
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Advances in CAD for VLSI |v ... | |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Simulation |0 (DE-588)4055072-2 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a CAD |0 (DE-588)4069794-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Simulation |0 (DE-588)4055072-2 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 1 | |5 DE-604 | |
| 689 | 2 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 2 | 1 | |a CAD |0 (DE-588)4069794-0 |D s |
| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Ruehli, Albert E. |e Sonstige |4 oth | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-012520462 | |
Datensatz im Suchindex
| _version_ | 1819253126702563328 |
|---|---|
| any_adam_object | |
| building | Verbundindex |
| bvnumber | BV009500750 |
| classification_rvk | ST 190 ZN 4950 |
| ctrlnum | (DE-599)BVBBV009500750 |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01403nam a2200433 ca4500</leader><controlfield tag="001">BV009500750</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">940401nuuuuuuuuxx |||| 00||| und d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0444878939</subfield><subfield code="9">0-444-87893-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0444878904</subfield><subfield code="9">0-444-87890-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0444878890</subfield><subfield code="9">0-444-87889-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV009500750</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakddb</subfield></datafield><datafield tag="041" ind1=" " ind2=" "><subfield code="a">und</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 190</subfield><subfield code="0">(DE-625)143607:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Circuit analysis, simulation and design</subfield><subfield code="c">ed. by A. E. Ruehli</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam u.a.</subfield><subfield code="b">North-Holland</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="490" ind1="0" ind2=" "><subfield code="a">Advances in CAD for VLSI</subfield><subfield code="v">...</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Simulation</subfield><subfield code="0">(DE-588)4055072-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Simulation</subfield><subfield code="0">(DE-588)4055072-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">CAD</subfield><subfield code="0">(DE-588)4069794-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ruehli, Albert E.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-012520462</subfield></datafield></record></collection> |
| id | DE-604.BV009500750 |
| illustrated | Not Illustrated |
| indexdate | 2024-12-23T17:29:41Z |
| institution | BVB |
| isbn | 0444878939 0444878904 0444878890 |
| language | Undetermined |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-012520462 |
| open_access_boolean | |
| publishDateSort | 0000 |
| publisher | North-Holland |
| record_format | marc |
| series2 | Advances in CAD for VLSI |
| spelling | Circuit analysis, simulation and design ed. by A. E. Ruehli Amsterdam u.a. North-Holland txt rdacontent n rdamedia nc rdacarrier Advances in CAD for VLSI ... Entwurf (DE-588)4121208-3 gnd rswk-swf Simulation (DE-588)4055072-2 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf CAD (DE-588)4069794-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Simulation (DE-588)4055072-2 s DE-604 Entwurf (DE-588)4121208-3 s CAD (DE-588)4069794-0 s Ruehli, Albert E. Sonstige oth |
| spellingShingle | Circuit analysis, simulation and design Entwurf (DE-588)4121208-3 gnd Simulation (DE-588)4055072-2 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4121208-3 (DE-588)4055072-2 (DE-588)4117388-0 (DE-588)4069794-0 |
| title | Circuit analysis, simulation and design |
| title_auth | Circuit analysis, simulation and design |
| title_exact_search | Circuit analysis, simulation and design |
| title_full | Circuit analysis, simulation and design ed. by A. E. Ruehli |
| title_fullStr | Circuit analysis, simulation and design ed. by A. E. Ruehli |
| title_full_unstemmed | Circuit analysis, simulation and design ed. by A. E. Ruehli |
| title_short | Circuit analysis, simulation and design |
| title_sort | circuit analysis simulation and design |
| topic | Entwurf (DE-588)4121208-3 gnd Simulation (DE-588)4055072-2 gnd VLSI (DE-588)4117388-0 gnd CAD (DE-588)4069794-0 gnd |
| topic_facet | Entwurf Simulation VLSI CAD |
| work_keys_str_mv | AT ruehlialberte circuitanalysissimulationanddesign |