A formal model of the processor memory interface
Abstract: "Pin limitations are increasingly a major problem in VLSI design. The majority of input/output pins are used for the memory interface. We present a mathematical model for memory access, predicting a pattern for the running time of processors with different memory structures. We then a...
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| Hauptverfasser: | , |
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| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Seattle, Wash.
1990
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| Schriftenreihe: | University of Washington <Seattle, Wash.> / Department of Computer Science: Technical report
90,1,15 |
| Schlagworte: | |
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| Zusammenfassung: | Abstract: "Pin limitations are increasingly a major problem in VLSI design. The majority of input/output pins are used for the memory interface. We present a mathematical model for memory access, predicting a pattern for the running time of processors with different memory structures. We then apply the model to several benchmarks from the literature, most of which follow predicted behavior well. Although one benchmark displays anomalous behavior, explained as an effect not included in the basic model, in the other cases, applying the model eliminates the need for much expensive and time-consuming simulation." |
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| Beschreibung: | 13 S. |