Logic synthesis and optimization
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| Format: | Buch |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Boston u.a.
Kluwer
1993
|
| Schriftenreihe: | The Kluwer international series in engineering and computer science
212 : VLSI, computer architecture and digital signal processing |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
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| 245 | 1 | 0 | |a Logic synthesis and optimization |c ed. by Tsutomu Sasao |
| 264 | 1 | |a Boston u.a. |b Kluwer |c 1993 | |
| 300 | |a XV, 375 S. |b Ill., graph. Darst. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 1 | |a The Kluwer international series in engineering and computer science |v 212 : VLSI, computer architecture and digital signal processing | |
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Logic circuits -- Computer-aided design | |
| 650 | 4 | |a Logic design -- Data processing | |
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Datensatz im Suchindex
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|---|---|
| DE-BY-TUM_katkey | 611226 |
| DE-BY-TUM_location | Mag LSB |
| DE-BY-TUM_media_number | 040003562387 TEMP2943905 |
| _version_ | 1822408432560373760 |
| adam_text |
CONTENTS
PREFACE
xiii
1
A NEW EXACT MINIMIZER FOR TWO-LEVEL
LOGIC SYNTHESIS
1
R. K. Brayion, P. C. McGeer, J. V. Sanghavi,
A. L. Sangiovanni-VincenteUi
1.1
Introduction
1
1.2
Notation
б
1.3
The Minimum Canonical Cover
8
1.4
Obtaining the Minimum Canonical Cover
13
1.5
Generating the Minimum Cover From the Minimum Canonical
Cover
23
1.6
Heuristic Minimization Procedures
24
1.7
Experimental Results
28
1.8
Related Work
29
2
A NEW GRAPH BASED PRIME
COMPUTATION TECHNIQUE
33
0. CoudeH, J. C.
Madre
2.1
Introduction
33
2.2
Definitions and Notations
34
2.3
The IPS Representation
36
2.4
Prime Computation of Boolean Functions
44
2.5
Prime Computation of Boolean
Vectorial
Functions
47
2.6
Experimental
Resulte
49
2.7
Conclusion
54
8
LOGIC SYNTHESIZERS, THE
TRANSDUCTION METHOD AND ITS
vi Logic
Synthesis and Optimization
EXTENSION, SYLON
59
5.
Munga
3.1
Introduction
59
3.2
Transduction Method
60
3.3
Logic Design of
MOS
Networks
72
3.4
New Logic Synthesis System, SYLON
75
3.5
Conclusions
83
NETWORK OPTIMIZATION USING
DON'T-CARES AND BOOLEAN RELATIONS
87
K-C. Chen, M. Fujita
4.1
Introduction
87
4.2
Multi-Level Combinational Networks
88
4.3
Permissible Functions, Don't-Cares, and Boolean Relations
89
4.4
Minimization Using Don't-Cares
90
4.5
Minimization Using Boolean Relations
97
4.6
Conclusion
105
MULTI-LEVEL LOGIC MINIMIZATION OF
LARGE COMBINATIONAL CIRCUITS BY
PARTITIONING
109
M. Fujita, Y. Maisunaga, Y.
Tamty
a,
K
-С.
Chen
5.1
Introduction
109
5.2
Boolean minimization
112
5.3
Partitioning for Boolean
minimizeis
119
6.4
Top-down application of two-way partitioning
122
5.б
Experimental results
122
5.6
Conclusions
124
A PARTITIONING METHOD FOR AREA
OPTIMIZATION BY TREE ANALYSIS
127
Y. Nakamura, K. Wakahaymhi, T. Fujite
6.1
Introduction
127
β
J
Logic Partition and Partial Collapsing
128
6.3
Parti»! Collapsing Baaed on Tree Structure Analysis
132
6.4
Logic Optimization
139
Contents
vii
6.5
Algorithms
139
6.6
Experimental Results
140
6.7
Conclusions
141
A NEW ALGORITHM FOR
0-1
PROGRAMMING BASED ON BINARY
DECISION DIAGRAMS
145
S-W. Jeong, F:
Sommai
7.1
Introduction
146
7.2
Preliminaries
147
7.3
The Algorithm
152
7.4
Experimental Results
162
7.5
Conclusions and Future Work
163
8
DELAY MODELS AND EXACT TIMING
ANALYSIS
167
P. C. McGeer,
A. Saldanha,
R.
К,
Brayton,
A. L. Sangiovanni-Vincenielli
8.1
Introduction
167
8.2
Ternary Delay Simulation and a Waveform Calculus
, 170
8.3
Delay Models
174
8.4
Combinational Timing Verification Under the XBDO Model
177
8.5
Combinational Timing Verification Under the XBD Model
183
8.6
Conclusions
188
9
CHALLENGES TO DEPENDABLE
ASYNCHRONOUS PROCESSOR DESIGN
191
T. Nanpa
9.1
Introduction
191
9.2
System Timing Failures
192
9.3
Delay Modeb
193
9.4
Asynchronous Architecture
197
9.5
Asynchronous Control and Data Transfer
199
9.6
Logie
Synthesis
206
9.7
Testing and Concurrent Checking
209
9.8
Metaetability
210
viii
Logic Synthesis and Optimization
9.9
Conclusions
210
10
EFFICIENT SPECTRAL TECHNIQUES FOR
LOGIC SYNTHESIS
215
D.
Verme, E.
A. Tmchienberg
10.1
Introduction
215
10.2
Transformation and Complexity of Boolean Functions
217
10.3
Efficient Spectral Methods for Logic Synthesis
223
10.4
Conclusion
230
11
FPGA DESIGN BY GENERALIZED
FUNCTIONAL DECOMPOSITION
233
T. Sasao
11.1
Introduction
233
11.2
Generalized Functional Decompoeition
235
11.3
Generalized Functional Decomposition ueing BDD
241
11.4
Design Method for
LUT Networi»
246
11.5
Experimental Results
254
11.6
Conclusions and Comments
256
12
LOGIC SYNTHESIS WITH EXOR GATES
250
T. Sasao
12.1
Introduction
259
12.2
Design Method of
ÁND-EXOR
circuits
261
12.3
Simplification of AND-EXOR expressions
268
12.4
Design Method for AND-OR-EXOR circuits
272
12.5
Experimental
Resulte
278
12.6
Conclusions and Comments
.
2S2
13
AND-EXQR EXPRESSIONS AND THEIR
OPTIMIZATION 2S7
T. Sasao
13.1
tatrodactioB
287
11.2
Severei
Classes of
ANÖ-EXOE
Шргвтют
2S8
13.3
Свяарлііаой
of Complexity
293
13.4
MmimKRtíon
of PSDKItOs
295
Contents ix
13.6
Experimental
Resulte
306
13.6
Conclusion
309
14
A GENERATION METHOD FOR EXOR-
SUM-OF-PRODUCTS EXPRESSIONS USING
SHARED BINARY DECISION DIAGRAMS
313
K. Yasnoka
14.1
Introduction
313
14.2
Preliminaries
314
14.3
Algorithm
314
14.4
Experimental Results
317
14.5
Conclusion
321
15
A NEW TECHNOLOGY MAPPING METHOD
BASED ON CONCURRENT FACTORIZATION
AND MAPPING
323
M.
Inamori,
A. Tahahara
15.1
Introduction
323
15.2
Concurrent Factorization and Mapping
327
15.3
Process of Technology Mapping
333
15.4
Experimental Results
337
15.5
Conclusions and Future work
339
16
GATE SIZING FOR CELL-BASED DESIGNS
341
W-P. Lee, Y-L. Lin
16.1
Introduction
341
16.2
Previous Works
344
16.3
The Theda.CBS System
344
16.4
Experimental Results
352
16.5
Summary and Future Works
355
A ABOUT THE AUTHORS
361 |
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| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
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| id | DE-604.BV008832770 |
| illustrated | Illustrated |
| indexdate | 2025-01-27T13:21:55Z |
| institution | BVB |
| isbn | 0792393082 |
| language | English |
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| physical | XV, 375 S. Ill., graph. Darst. |
| publishDate | 1993 |
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| publisher | Kluwer |
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| series | The Kluwer international series in engineering and computer science |
| series2 | The Kluwer international series in engineering and computer science |
| spelling | Logic synthesis and optimization ed. by Tsutomu Sasao Boston u.a. Kluwer 1993 XV, 375 S. Ill., graph. Darst. txt rdacontent n rdamedia nc rdacarrier The Kluwer international series in engineering and computer science 212 : VLSI, computer architecture and digital signal processing Datenverarbeitung Logic circuits -- Computer-aided design Logic design -- Data processing Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf (DE-588)1071861417 Konferenzschrift gnd-content Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s DE-604 Sasao, Tsutomu 1950- Sonstige (DE-588)122406427 oth The Kluwer international series in engineering and computer science 212 : VLSI, computer architecture and digital signal processing (DE-604)BV023545171 212 Digitalisierung TU Muenchen application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=005839660&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Logic synthesis and optimization The Kluwer international series in engineering and computer science Datenverarbeitung Logic circuits -- Computer-aided design Logic design -- Data processing Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd |
| subject_GND | (DE-588)4131023-8 (DE-588)4121208-3 (DE-588)1071861417 |
| title | Logic synthesis and optimization |
| title_auth | Logic synthesis and optimization |
| title_exact_search | Logic synthesis and optimization |
| title_full | Logic synthesis and optimization ed. by Tsutomu Sasao |
| title_fullStr | Logic synthesis and optimization ed. by Tsutomu Sasao |
| title_full_unstemmed | Logic synthesis and optimization ed. by Tsutomu Sasao |
| title_short | Logic synthesis and optimization |
| title_sort | logic synthesis and optimization |
| topic | Datenverarbeitung Logic circuits -- Computer-aided design Logic design -- Data processing Logische Schaltung (DE-588)4131023-8 gnd Entwurf (DE-588)4121208-3 gnd |
| topic_facet | Datenverarbeitung Logic circuits -- Computer-aided design Logic design -- Data processing Logische Schaltung Entwurf Konferenzschrift |
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