The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990
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| 245 | 1 | 0 | |a The proceedings of the European Design Automation Conference |b Glasgow, Scotland, 12 - 15 March 1990 |
| 264 | 1 | |a Washington, DC |b IEEE Computer Soc. Press |c 1990 | |
| 300 | |a XX, 683 S. |b graph. Darst. | ||
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The Proceedings of
The (European
Design Automation
Cc Oo nfe re n Cc e Nachrichtentechnische Bibliothek
THD
Inv -Nr :
Glasgow, Scotland
12-15 March 1990 AA ZA TO
Sponsored by
IEEE Computer Soclety Order Number 2024 EDAC Association
Library of Congress Number 89-46211
ISBN 0-8186-2024-2 In association with
SAN 264-620-X IEEE Computer Society
@ amp; IEEE COMPUTER SOCIETY amp; ARD ELECTRONGS ENGINEERS MC SOCIETY cn
\eee PRESS
iii
Table of Contents
Foreword uenessnsssnnsnnnnnnnnsnsssususnnsnsnnnsnsnnnsunnnnnnnunennsusunnnnnnnsnnnssonnnsnsnsnnnnenssnsansnensssnssnssnssnnssensarsanne nennen iti
Conference COmmMittee ccsssccessssseescccscssssansesesssscssscecesscssenssacseserecaseseeseseesecenseeesseecuceessssvesssesseeuaaes v
Technical Programme Committee ‚vi
Tutorials zscecsesasnsonnesnenesssnnennne oe Vii
Panel Session enereosnensasoansensanssronunenunsnnunnssnensessonnenssnenenenunssssssonnnnssusasennssnsnsnsnsnnsennssnssnsansessnsstenene viii
EDAC 91 Call for Papers ccccscccsesscscessessessescscesessvssesssssceconssasssseessseneussessassseeescesseeereenessess ix
Session 1A: Tools for Testing
Moderators: R G Bennetts, Bennetts Associates, UK
B Courtois, IMAG/TIM3, France
1A 1 Generation of Embedded RAMs with Built-In Test Using Object-Oriented Programming 0 2
M Zimmermann and M Geilert
1A 2 ASTA - An Integrated System for BIST Analysis and Automatic Test Generation cccccssssssssseess 7
S Hodgson, L Theobald, W B Hughes and R J Illman
1A 3 Tools and Devices Supporting the Pseudo-Exhaustive Test 13
S Hellebrand and H-J Wunderlich
1A 4 Development of Test Programs with the Aid of a Tester-Oriented Pattern Language c csesesseseseers 18
M Klimke, C Winkelmeyr and H Eichinger
Session 1B: Databases and Frameworks
Moderators: J Brouwers, EDA Systems, USA
J Lecourvoisier, CNET, France
1B 1 A Database Interface for Phased Tool Integration ccscessssssesssesessssesseeesseesstasstneeesseacaceesseeerens 24
T Kathofer, W Fox, D Nolte, K Pielsticker, R Quester, F Rupprecht and M Schrewe
1B 2 On the Architecture of a CAD Framework: The NELSIS Approach cccccsecsossssssssssceseersseeseeeee 29
P van der Wolf, P Bingley and P Dewilde
1B 3 Design Data Management in a Distributed Hardware Environment cccssessssssessecssecetceceeteeeecees 34
G W Sloof, P Bingley, P Dewilde, TGR van Leuken and P van der Wolf
1B 4 The NMP-CADLAB Framework - a Common Framework for Tool Integration and Development 39
J Haabma and B Steinmueller
Session 1C: Formal Verification
Moderators: G Milne, University of Strathclyde, UK
F Anceau, BULL, S A, France
1C 1 On the Notion of the Normal Form Register-Level Structures and Its Applications in
Design-Space Exploration csccssssssssssresssseeseeteanescseesecscusonseenseascsseasssenseasecssesensuassesseranceenanes 46
R Vemuri
1C 2 Functional Semantics of Microprocessors at the Microprogram Level and Correspondance
with the Machine Instruction Level csssssssssssssssessssssccsssssessssessssessesscesssssesersscseseseansseonssee® 52
H Collavizza
1C 3 Formal Boolean Manipulations for the Verification of Sequential Machines
O Coudert, C Berthet and J C Madre
1C 4 Correctness Proofs of Parameterized Hardware Modules in the Cathedral-II Synthesis Environment
D Verkest, L Claesen and H De Man
Session 2A: Scheduling and Allocation |
Moderators: W Rosenstiel, FZ, FRG
H De Man, IMEC, KU Leuven, Belgium
2A 1 Synthesis of Delay Functions in DSP Compilers scccsscssssscssecsonaresssccesecsenscaeceneneneneaseesoesees
A Delaruelle, O McArdle, J van Meerbergen and C Niessen
2A 2 A Branch-and-Bound Method for Optimal Transformation of Data Flow Graphs for
Observing Hardware Constraints cssssssscscsssecsssecssssecsesssscssesssscesessscsssssssecsscsesensseserseenersees 73
W Grass
24 3 SCHALLOC: An Algorithm for Simultaneous Scheduling and Connectivity Binding in a
Datapath Synthesis System ::cccsscccssssscsssssscsesscescessssseeceesecsecssscsenansensaccocaecuseeseneeesseeeeret 78
N Berry and B M Pangrie
2A 4 A New Approach to Pipeline Optimisation c csssenssenneoonneennnananonsnnnnnannononnannaneonnnanenanssneren sans
D J Mallon and P B Denyer
Session 2B: Simulation Languages
Moderators: G Musgrave, Brunel University, UK
P Moorby, Gateway Design Automation, USA
2B 1 NETHDL: Abstraction of Schematics To High-Level HDL nnccorscssnnesssonnoneensossonenenennnsannennene
D Fischer, Y Levhari and G Singer
2B 2 Comparison of Implementations of Real Arithmetic in ELLA and VHDL cccccccsscserseeeresseseeees
C O Newton and M G Hill
2B 3 MINT - a VHDL Simulation System c:ccsssscsssececeeeseencnerecesessecsnsacansessecceeeansseeeeneneeneces
M Altmae
2B 4 Structured Analysis and VHDL in Embedded ASIC Design and Verification ussesesnesesrsnrsrserneneee
T Tikkanen, T Leppanen and J Kivela
Session 2C: Cell Generators
Moderators: R Otten, Technical University of Delft, The Netherlands
G Koetzle, IBM, FRG
2C 1 An Algebraic Model for Design Space with Applications to Function Module Generation - --
A Tyagi
2C 2 Transistor Placement and Interconnect Algorithms for Leaf Cell Synthesis cccssscccccesesseecsees 119
M Lefebvre, C Chan and G Martin
2C 3 A Flexible Hierarchical 3-D Module Assemblet ccsscssscesssesescescsssssessesscssscersscseaese 124
R Dutta, M Marks, C Morrissey, R Rao and L Sapiro
2C 4 PARAGON: A New Package for Gate Matrix Layout Synthesis : 129
R Burgess and C Wouters
Session 3A: Scheduling and Allocation Il
Moderators: H De Man, IMEC, KU Leuven, Belgium
W Rosenstiel, FZ Karlsruhe, FRG
3A 1 A Neural Net Based Self Organising Scheduling Algorithm ccccsssccccsecceeececesescceceussseuseneeses 136
A Hemani and A Postula
3A 2 Interconnect Optimisation During Data Path Allocation uensersessnsssssosonssorsnssnnsnsssusnnasanenenennen 141
L Stok
3A 3 Matching System and Component Behaviour in MIMOLA Synthesis Tools scssssscsssssrensers 146
P Marwedel
3A 4 Redesign Using State Splitting ucesersesssnuenusnunensnnunsnunansnonsnnnnnnnnnnnnnnnnnnsnonsnsnsnenensnenunssnessennnne 157
R Camposano andR A Bergamaschi
Session 3B: Description of Design Systems and Methodologies
Moderators: J Lecourvoisier, CNET, France
J Brouwers, EDA Systems, USA
3B 1 Silicon Compilation of Switched-Capacitor Networks ueessosessssssonensnenusnsonunnanenssnensnnsnnnonnnnennnnnnne 164
M Negahban and D Gajski
3B 2 An Intelligent Design System for Analog Integrated Circuits cccssesscssssssssecccssserensessecsceeerens 169
G Gielen, K Swings and W Sansen
3B 3 A Graphical System for Hierarchical Specifications and Checkups of VLSI Circuits cccssscssesess 174
B Becker, T Burch, G Hotz, D Kiel, R Kolla, P Molitor,
HG Osthof, G Pitsch and U Sparmann
3B 4 Automatic Knowledge Acquisition in a Digital Circuit Design System nssessscensnensnsssnenssssonnen 180
J-G Wu
Session 3C: Compaction and Circuit Packing
Moderators: J-P Le Bouquin, IBM, France
J-P Tual, Bull SA, France
3C 1 Optimal Via-Shifting in Channel Compaction eurseerssnssuennsssnsesunnsnennnesunnsonnsnnnsonnnnnannnsonnsnonnnenenn 186
Y Cai and D F Wong
xiii
3C 2 Adaptive Cluster Growth (ACG): A New Algorithm for Circuit Packing in Rectilinear Region 191
C M Kyung, J M Widder and D A Mlynski
3C 3 An Efficient Two-Dimensional Compaction Algorithm for VLSI Symbolic Layout 196
S-J Wei, J Leroy and R Crappe
3C 4 CACTUS: A Symbolic CMOS Two-Dimensional Compactor c ucssssscssssssscescessscsssssereeseooes 201
T Perez-Segovia and A-F Joanblang
Session 4A: Combinational Logic Design Optimization
Moderators: F Theeuwen, Eindhoven Technical University, The Netherlands
E Van Utteren, Philips Research Laboratories, The Netherlands
4A 1 An Iterative Algorithm for the Binate Covering Problem :csssssssssssscersecscecssssceecueesereaeseeeee 208
M Pipponii and F Somenzi
4A 2 Technology Mapping Using Boolean Matching and Don't Care Sets cesssesnsscceccenneseeenceerenecs 212
F Mailhot and G De Micheli
4A 3 Gate Sizing in MOS Digital Circuits with Linear Programming c0cc:cccssesssssceseseseeeeereerenees 217
MRCMBerkelaarand JAG Jess
4A 4 A New Synthesis Technique for Multilevel Combinational Circuits uesensessssseesenanenessnnnnsnnseonsnenen 222
L Diaz-Olavarrieta and S G Zaky
Session 4B: Simulation |
Moderators: M Glesner, Darmstadt, FRG
G Musgrave, Brunel University, UK
4B 1 An Event-Driven Transient Simulation Algorithm for MOS and Bipolar Circuits ::ccereseeee 230
D Patrick and C Lyden
4B 2 PLATO: A New Piecewise Linear Simulation Tool urereserseessseensnenennnunnennronnsannnsnsssnsnanssernenen 235
MT van Stiphout, JTJ van Eijndhoven and H W Buurman
4B 3 Event-Driven Behavioural Simulation of Analogue Transfer Functions :sscsesssescceessseesereseanees 240
RA Cottrell
4B 4 A Combined Waveform Relaxation - Waveform Relaxation Newton Algorithm
for Efficient Parallel] Circuit Simulation c sccecescsesencenscececeneeneceaessenseasoasensesscereneaneneea gees 244
P Odent, L Claesen and H De Man
Session 4C: Floorplanning
Moderators: J-P Tual, BULL SA, France
R Otten, Technical University of Delft, The Netherlands
4C i CHEOPS: An Integrated VLSI Floor Planning and Chip Assembly System
Implemented in Object Oriented Lisp uueeuennennsennnnnnenneneneeeenennenseennnsnonernessonsonssssenessnanss nen nn 250
C Masson, D Barbier, R Escassut, D Winer, G Chevallier and P F Zeegers
4C 2 A VLSI Floorplanner based on “Balloon” Expansion 257
N Yonezawa, N Nishiguchi, A Etani, F Tsukuda and R Hashishita
xiv
4C 3 A System for Floorplanning with Hierarchical Placement and Wiring cccssssssssscsssssssscsssssesens 262
K McCullen, J Thorvaldson, D Demaris and P Lampin
4C 4 ACCORDO: Second Generation Floor Planning cccccccscssssccccccescccscccssscscccscossserenssscseccess 266
G Arato, G Bussolino, A M Fiammengo and R Manione
Session 5A: High Level Synthesis Systems
Moderators: R Camposano, IBM, USA
L Philipson, University of Lund, Sweden
5A 1 Open-ended System for High-Level Synthesis of Flexible Signal Processors ssccccecsesecsesseeees 272
D Lanneer, F Catthoor, G Goossens, M Pauwels, J van Meerbergen and H De Man
5A 2 System Synthesis using Behavioural Descriptions scceccscccrcrsecccerecsnecceececeeseeseeeseseseeeenerens 277
H Kramer and W Rosenstiel
5A 3 Towards a Global Solution to High Level Synthesis Problems cscccseseseeeee nnssusssnussnsssssesenen 283
A Safir and B Zavidovique
Session 5B: Simulation Il
Moderators: G Saucier, JINPG, France
AP Ambler, Brunel University, UK
5B 1 The EVE Companion Simulator ccccccscesscsscesececsceseesseesseeesessseseseeoeeceecereesscesseeenen na saseeeees 290
DK Beece, R Damiano, G Papp and R Schoen
5B 2 An Incremental Functional Simulator Implemented on a Network of Transputer sssseseseeee 296
K Dimond and S Hassan
5B 3 Derivation of Signal Flow for Switch-Level Simulation neessssnsssessnnensnsnonessennnorenonnnnenenensenennnn 301
DT Blaauw, D G Saab, J Long and J Abraham
5B 4 Multirate Integration in a Direct Simulation Method ueeneesenenensenesonsnsssnennnnenennnnsnnnnnsennnnannnnonnen 306
J TJ van Eijndhoven, M T van Stiphout and H W Buurman
Session 5C: Placement
Moderators: H Beke, EDC, Belgium
M Burstein, Descartes Automation Systems, USA
5C 1 An Efficient Placement Method for Large Standard-Cell and Sea-of-Gates Designs ccccccsecesesene 312
HJ Kappen and FMJ de Bont
5C 2 VLSI-Placement Based on Routing and Timing Information :cscsccsessssssseseescsecsecanscussensesess 317
J Garbers, B Korte, H J Promel, E Schwietzke and A Steger
5C 3 Optimal Slicing of Plane Point Placementts csscsscsssscessseseseesssssseecccecessessessserescessesatenseass 322
LP P P van Ginneken and RHJM Otten
5C 4 A Gate-Matrix Oriented Partitioning Approach for Multilevel Logical Networks cccccsesceseeseseee 327
F H Huentemann and U G Baitinger
Session 6A: Delay and CMOS Testing
Moderators: P Teixeira, INESC, Portugal
K Baker, Philips Research, The Netherlands
6A 1 On the Fault Coverage of Delay Fault Detecting Tests ccccccsccsssssssesecceccseseccecessevecsenenseneeese® 334
AK Pramanick and S M Reddy
6A 2 Some Relations Between Delay Testing and Stuck-Open Testing in CMOS Cireuits neseee 339
R David, S Rahal and J-L Rainard
6A 3 Robust Tests for Stuck-Open Faults and Design for Testability of Reconvergent Fan-Out
CMOS Logic Networks uensesssnsssnssenssnenssenssenssonersenssensssnnsnnssnsnnannensensnonansnnennssnstssnnsnn nennt 344
F Darlay and B Courtois
6A 4 Detection of Multiple Input Bridging and Stuck-on Faults in CMOS Logic Circuits
Using Current Monitoring :ccsecccesscsesseseeesscesesaccessssssececssescocontececesencececececeeeensoonaaeeree 350
NK Jha and Q Tong
Session 6B: Databases and Datastructuring
Moderators: J Janse, Philips Research Laboratories, The Netherlands
B Steinmuelier, CADLAB, FRG
6B 1 A Data-structuring Technique for Gridded VLSI Layouts sc2ssscccsssecesessnnerececeeeceseessnsananeeoen 356
S M Haider and P H Ang
6B 2 An Object-Oriented Persistent Database Interface for CAD 363
MN Sim and P M Dewilde
6B 3 Design Management with a Design Environment ueseessssssnsnnsennenssnunennennsenennsnenennnenaansanonse nen 368
P Drescher, J Miller and G Schulz
6B 4 A Design Representation for High Level Synthesis unenenssenoneneeneennen 374
MRK Patel
Session 6C: Physical Verification and Simutation
Moderators: R Gerber, CNET, France
D Storey, TI, UK
6C 1 Hierarchical Layout Verification for Submicron Designs sssssecesercesseresroratonseeseserseneeaseneees 382
W Meier
6C 2 CIRCE: A Program for Parasitic Parameter Extraction ssescecesecessencececceerenseeeeosansesseeseenenees 387
C Marazzini , M Santomauro and M Taliercio
6C 3 An Improved Layout Verification Algorithm(LAVA) c:csscsccsccecsesscscscesensensensenaenseneasersecseoonene 391
M S Abadir and J Ferguson
6C 4 Simulation Based Verification of Register-Transfer Level Behavioural Synthesis Tools 396
R Ernst, 5 Sutarwala, J-Y Jou and M Tong
Session 7A: Low-Level Fault Modelling and Test Generation
Moderators: V Agrawal, AT amp;T Bell Laboratories, USA
R G Bennetts, Bennetts Associates, UK
7A 1 A New Switch-Level Test Pattern Generation Algorithm Based on Single Path
Over a Graph Representation osennossnenennananasonnnnnnnnnnnnnnnansenununnanunnenssssssenssnenenensesnsesusnennse
C Ferrer, J Oliver and E Valderrama
7A 2 Fault Modelling and Fault Equivalence in CMOS Technology ccccccscscsssccsessssersesesseeecsescersere
M L Flottes, C Landrault and S Pravossoudovitch
7A 3 A Strategy for Testability Enhancement at Layout Level
J P Teixeira, I C Teixeira, CFB Almeida, F M Goncalves, J Goncalves and R Crespo
7A 4 Accelerated Test Pattern Generation by Cone Oriented Circuit Partitioning ccccsccccccscscceevevees
T Gruning, U Mahlstedt, W Daehn and C Ozcan
Session 7B: Selected Topics in CAD Systems
Moderators: M Vanzi, SGS-Thomson, Italy
P Dewilde, Technical University of Delft, The Netherlands
7B 1 Economics of Point Acceleration cccccssscsssrscsscescescosssnscceecesssescnsseresessececesscecsesereseseseces
E W Burger and G Dedene
7B 2 Logic Optimization on a Concurrent Processing Computer ccscesscesesececcecececeesceeecueceescecones
F Theeuwen
7B 3 The Use of Computer-Aided Software Engineering Technology in Systems
and Software Design sssesesccccsstorcccccnsnesstecsceceuavessesenscenenssescedsenansnsenserssebosersassenenessenees
DF Burrows
7B 4 Rapid Prototyping Using High Density Interconnects ennssonssssnessonsoursnesnnsnennneonennanansannannanne
R Hartley, K Welles II, M Hartman, P Delano and A Chatterjee
Session 7C: Routing
Moderators: M Burstein, Descartes Automation Systems, USA
D Storey, T/, UK
7C 1 MOLE - A Sea-of-Gates Detailed Router cccscssssssscecsssecsesecssssesscsesesseescstssesessscessensuseseae
A Srinvasan and E § Kuh
7C 2 Channel Routing With Non-Terminal Doglegs ccccsececscseseeeeteveceseeaeeeeeeaensassesasecescececeses
B Preas
7C 3 On the k-Layer Planar Subset and Via Minimization Problems ssecssssessssssscssnssccceeecees
J Cong and C L Liu
7C 4 Path Search on Rectangular Floorplan ssccssscccsscsssansccesessssevsssessarscanseeusucsesueneuceeseesevesans
C S Ying, X L Hong, E Q Wang and JSL Wong
Session 8A: Test Pattern Generation and Fault Simulation
Moderators: P Teixeira, INESC, Portugal
W Daehn, Universitat Hannover, FRG
8A 1 Diagnosis Oriented Test Pattern Generation sssssecsessccccesecsssessrvevecesceenectsenessaneseeesceneecessneseee
P Camurati, A Lioy, P Prinetto and M Sonza Reorda
8A 2 PROOFS: A Super Fast Fault Simulator for Sequential Circuits ccccccccssoesssreersentorssessaenerse
W-T Cheng and J H Patel
8A 3 High Level Test Generation Using Data Flow Descriptions ccccssseresensenececnnsnseeeseneasanavensees
K Roy and J A Abraham
8A 4 Experience in Functional-Level Test Generation and Fault Coverage in a
Silicon Compiler cccssssssssssccsccsescvsvesnensanancnsecssssensssusceescesaceasucresagaasssecsenosscsensesseeeeeeenes
C Jay
Session 8B: Procedural Interfaces
Moderators: B Steinmueller, CADLAB, FRG
M Vanzi, SGS-Thomson, Italy
8B 1 SPI: An Open Interface Integrating Highly Interactive Electronic CAD Tools scccccseccersneeseerseese
J P Schupp, J Cockx, L Claesen and H De Man
8B 2 A Procedural Interface to CAD Data Based on EDIP ccccsscccecececccecsceusrscseenenescacenenenacaqanenses 496
TC O Young and H J Kahn
8B 3 Ghost/Spook - User Interface and Process Management in the PACE Framewolk scseesesescenerees 501
P Reis dos Santos, H Sarmento and L Vidigal
8B 4 Storage Mechanism for VHDL Intermediate Form sccccscsssecceeeeeeescncseseecsenensesseeaqaasousssasenes 506
B Poterie
Session 8C: Timing Analysis and Verificaton
Moderators: L Claesen, IMEC, Belgium
C Trullemans, UC Louvain, Belgium
8C 1 Formal Verification of Timing Conditions 2 2cssus0snussnsnesenssennnsnnsnnnnsn nenn nnsneneensnnanenneeen
H Eveking and C Mai
8C 2 SLOCOP-11: A Versatile Timing Verification System for MOS VLST eaenssesuossesssnesnsensnernonert 518
P Johannes, P Das, L Claesen and H De Man
8C 3 Automatic Generation of Timing Specifications for CMOS Transistor Subnetworks ereeesenenenennerrenr 524
R Tjarnstrom
8C 4 Path Runner: An Accurate and Fast Timing Analyser ueessnessonensensnnnenanonnenenserrosna nenne nnensannnt
D Deschacht, P Pinede, M Robert and D Auvergne
Session 9A: Finite State Machine Synthesis I
Moderators: L Philipson, University of Lund, Sweden
R Camposano, JBM, USA
9A 1 Efficient Suboptimal State Assignment for Large Sequential Machines 536
L Jozwiak
9A 2 Multi-Level Synthesis on PALS cc sceessesssesssseeseesscesssneessssessessnecvsceesetsesssessuserseasessaeecenee 542
G Saucier, P Sicard and L Bouchet
9A 3 State Assignment for Controllers for Optimal Area Implementation scccscsoccessssecssssesceneeees S47
G Saucier, C Duff and F Poirot
9A 4 A New Method for the State Reduction of Incompletely Specified Finite Sequential Machines 552
M J Avedillo, J M Quintana and J L Huertas
Session 9B: Simulation Modelling
Moderators: A P Ambler, Brunel University, UK
S Murai, Mitsibushi, Japan
9B 1 Transmission Gate Delay Models for Circuit Optimization 558
V Eisele, B Hoppe and O Kiehl
9B 2 An Accurate Model for Ambiguity Delay Simulation ccccccssccsccsscrcscsssrstsrsrsserscessersssssseneenes 563
T H Krodel and K J Antreich
9B 3 Switch-Level Timing Models in the MOS Simulator BRASIL ccsesesccceanssncececeseecscececessceeas 568
H Warmers, D Sass and E-H Horneber
9B 4 Software Architecture of Universal Hardware Modeler ccccccccscccecsncseorssccrsssscseseesessscsseesessereees 573
N F Kelly and H E Stump
9B 5 Design to Test Migration: a Tester and a Simulator ccccscscesecescceeeccecccnseceeescceuecereestereeseenens 578
G F Taylor
Session 9C: Physical Design Optimization
Moderators: C Masson, BULL SA, France
J Jess, TU Eindhoven, The Netherlands
9C 1 Solution of a Module Orientation and Rotation Problem \ 584
X Yaoand CLLiu
9C 2 A New Algorithm for Transistor Sizing in CMOS Circuits 589
C-H A Wu, N V Zanden and D Gajski
9C 3 Cell Based Performance Optimization of Combinational Circuits 2 -20seanessenensnnessnonsensanenenanenn 594
U Hinsberger andR Kolla
9C 4 A Dynamic Programming Approach to the Power Supply Net Sizing Problem ccccccsscsesscecsees 600
R Kolla
9C 5 NAUTILE: A Safe Environment for Silicon Compilation ssccsssssscscssssctsssssseccsesesseneecense 605
P Bondono, AA Jerraya, A Hornik, B Courtois and D Bonifas
xix
Session 10A: Finite State Machine Synthesis - Il
Moderators: F Theeuwen, Eindhoven Technical University, The Netherlands
E Van Utteren, Philips, The Netherlands
10A 1 An Architecture for Synthesis of Testable Finite State Machines cssssssscesssescssceessssesoeees 612
V D Agrawal and K-T Cheng
10A 2 CGE: Automatic Generation of Controllers in the CATHEDRAL-II Silicon Compiler 617
J Zegers, P Six, J Rabaey and H De Man
10A 3 Fuzzy Specification of Finite State Machines :ccssssccssssssscesesnssescescecessaaseceesnensseeesereneeeoe 622
SJ Mensch and H M Lipp
Session 10B: Verification and PLA Testing
Moderators: R David, Laboratoire d'Automatique de Grenoble, France
J Mucha, Hannover University, FRG
10B 1 The Effectiveness of Different Test Sets for PLAS ccccccccssssssecccesssnsensesctensesesesececsencesoneoneed 628
PC Maxwell and H-J Wunderlich _
10B 2 Fully Testable PLA Design with Minimal Extra Input mesnsensenennensennnsnssnnsenenensnnsononsnene 633
C W Chiou and T C Yang
10B 3 PEST - A Tool for Implementing Pseudo-Exhaustive Self Test cssscessececerenseneereesssaseeeneeres 639
E Wu and P W Rutkowski
10B 4 Design for Verification Testability unennensnerssennonennnnennnnneonansnnnnnsnonnnannsnoneensnnanennesensn ss orten 644
A Krasniewski
Session 10C: Novel Approaches in Placement
Moderators: G Koetzle, /BM, FRG
J-P Le Bouquin, /BM, France
10C 1 Pre-placement of VLSI Blocks through Learning Neural Networks sccsscsercesssecsenenseneatennenennes 650
D D Caviglia, G M Bisio, F Curatelli, L Giovannacci and L Raffo
10C 2 Fuzzy Set Based Initial Placement for IC Layout nenesnsnsesnssssensssnsnnnesnenessensennenenensennnsansennnen 655
M Razaz and J Gan
10C 3 GASP - A Genetic Algorithm for Standard Cell Placement s:csccssesrsececserseserssensateerecesenn cen 660
K Shahookar and P Mazumder
10C 4 A New Clustering Approach and Its Application to BBL Placemenit sscssssesscserssneeeesevereraseees 665
MY Yu, X L Hong, Y E Lien, Z Z Ma, J G Bo and W J Zhuang
POSter SUMMATIES occ cccscscscensssstssstsssescssseessssesecssessseeneeseesssseseeensoseeerenenees 671
Author [mdex 0 ccccccnseccccscoccnensesscvecsccesvencesscecsssensesevscnsscssscensussecsvacsecceseananssaseesssuccseeeceesess 681 |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
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| illustrated | Illustrated |
| indexdate | 2025-01-27T13:22:10Z |
| institution | BVB |
| institution_GND | (DE-588)1233184-3 |
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| language | English |
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| publisher | IEEE Computer Soc. Press |
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| spelling | EDAC 1 1990 Glasgow Verfasser (DE-588)1233184-3 aut The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 Washington, DC IEEE Computer Soc. Press 1990 XX, 683 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Cad (congressos) larpcal Computer-aided design Congresses CAD (DE-588)4069794-0 gnd rswk-swf (DE-588)1071861417 Konferenzschrift 1990 Glasgow gnd-content CAD (DE-588)4069794-0 s DE-604 HEBIS Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=004036681&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 Cad (congressos) larpcal Computer-aided design Congresses CAD (DE-588)4069794-0 gnd |
| subject_GND | (DE-588)4069794-0 (DE-588)1071861417 |
| title | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 |
| title_auth | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 |
| title_exact_search | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 |
| title_full | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 |
| title_fullStr | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 |
| title_full_unstemmed | The proceedings of the European Design Automation Conference Glasgow, Scotland, 12 - 15 March 1990 |
| title_short | The proceedings of the European Design Automation Conference |
| title_sort | the proceedings of the european design automation conference glasgow scotland 12 15 march 1990 |
| title_sub | Glasgow, Scotland, 12 - 15 March 1990 |
| topic | Cad (congressos) larpcal Computer-aided design Congresses CAD (DE-588)4069794-0 gnd |
| topic_facet | Cad (congressos) Computer-aided design Congresses CAD Konferenzschrift 1990 Glasgow |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=004036681&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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