VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling

Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophistica...

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Veröffentlicht in:ACM transactions on reconfigurable technology and systems 2020-06, Vol.13 (2), p.1-55, Article 9
Hauptverfasser: Murray, Kevin E., Petelin, Oleg, Zhong, Sheng, Wang, Jia Min, Eldafrawy, Mohamed, Legault, Jean-Philippe, Sha, Eugene, Graham, Aaron G., Wu, Jean, Walker, Matthew J. P., Zeng, Hanqing, Patros, Panagiotis, Luu, Jason, Kent, Kenneth B., Betz, Vaughn
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container_issue 2
container_start_page 1
container_title ACM transactions on reconfigurable technology and systems
container_volume 13
creator Murray, Kevin E.
Petelin, Oleg
Zhong, Sheng
Wang, Jia Min
Eldafrawy, Mohamed
Legault, Jean-Philippe
Sha, Eugene
Graham, Aaron G.
Wu, Jean
Walker, Matthew J. P.
Zeng, Hanqing
Patros, Panagiotis
Luu, Jason
Kent, Kenneth B.
Betz, Vaughn
description Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated highquality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3x faster) and memory footprint (3.3x lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools-showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.
doi_str_mv 10.1145/3388617
format Article
fullrecord <record><control><sourceid>webofscience_cross</sourceid><recordid>TN_cdi_webofscience_primary_000583746000004CitationCount</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>000583746000004</sourcerecordid><originalsourceid>FETCH-LOGICAL-c187t-94812f80a506d5b795b7a2000bbdae7d139e8438e74962f4e39b36fd46bf35833</originalsourceid><addsrcrecordid>eNqNkNFLwzAQxoMoOKf4L-TNB6kmS5qkvpXqNmGiyPS1pO1li3TNSFJE_3o7NvbswXH38Pu-4z6Erim5o5Sn94wpJag8QSOaMZFITvnpcSfiHF2E8EWIYELxEZp_Lt-xesBzu1onW_DG-Y3uasBF_oh11-CiD9Ft7K-uWsDTt1mOc1-vbYQ69h7wi2ugbW23ukRnRrcBrg5zjD6mT8tinixeZ89FvkhqqmRMMq7oxCiiUyKatJLZ0HpCCKmqRoNsKMtAcaZA8kxMDAeWVUyYhovKsFQxNkY3e9_auxA8mHLr7Ub7n5KSchdAeQhgINWe_IbKmVBbGP460sPJwU5yQXbFCxt1tK4rXN_FQXr7fyn7A_CBa2s</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling</title><source>Access via ACM Digital Library</source><source>Web of Science - Science Citation Index Expanded - 2020&lt;img src="https://exlibris-pub.s3.amazonaws.com/fromwos-v2.jpg" /&gt;</source><creator>Murray, Kevin E. ; Petelin, Oleg ; Zhong, Sheng ; Wang, Jia Min ; Eldafrawy, Mohamed ; Legault, Jean-Philippe ; Sha, Eugene ; Graham, Aaron G. ; Wu, Jean ; Walker, Matthew J. P. ; Zeng, Hanqing ; Patros, Panagiotis ; Luu, Jason ; Kent, Kenneth B. ; Betz, Vaughn</creator><creatorcontrib>Murray, Kevin E. ; Petelin, Oleg ; Zhong, Sheng ; Wang, Jia Min ; Eldafrawy, Mohamed ; Legault, Jean-Philippe ; Sha, Eugene ; Graham, Aaron G. ; Wu, Jean ; Walker, Matthew J. P. ; Zeng, Hanqing ; Patros, Panagiotis ; Luu, Jason ; Kent, Kenneth B. ; Betz, Vaughn</creatorcontrib><description>Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated highquality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3x faster) and memory footprint (3.3x lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools-showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.</description><identifier>ISSN: 1936-7406</identifier><identifier>EISSN: 1936-7414</identifier><identifier>DOI: 10.1145/3388617</identifier><language>eng</language><publisher>NEW YORK: Assoc Computing Machinery</publisher><subject>Computer Science ; Computer Science, Hardware &amp; Architecture ; Science &amp; Technology ; Technology</subject><ispartof>ACM transactions on reconfigurable technology and systems, 2020-06, Vol.13 (2), p.1-55, Article 9</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>true</woscitedreferencessubscribed><woscitedreferencescount>136</woscitedreferencescount><woscitedreferencesoriginalsourcerecordid>wos000583746000004</woscitedreferencesoriginalsourcerecordid><cites>FETCH-LOGICAL-c187t-94812f80a506d5b795b7a2000bbdae7d139e8438e74962f4e39b36fd46bf35833</cites><orcidid>0000-0002-2578-2147 ; 0000-0002-4157-8584 ; 0000-0003-2764-823X ; 0000-0002-8535-3432 ; 0000-0002-8151-8359</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>315,782,786,27931,27932,28255</link.rule.ids></links><search><creatorcontrib>Murray, Kevin E.</creatorcontrib><creatorcontrib>Petelin, Oleg</creatorcontrib><creatorcontrib>Zhong, Sheng</creatorcontrib><creatorcontrib>Wang, Jia Min</creatorcontrib><creatorcontrib>Eldafrawy, Mohamed</creatorcontrib><creatorcontrib>Legault, Jean-Philippe</creatorcontrib><creatorcontrib>Sha, Eugene</creatorcontrib><creatorcontrib>Graham, Aaron G.</creatorcontrib><creatorcontrib>Wu, Jean</creatorcontrib><creatorcontrib>Walker, Matthew J. P.</creatorcontrib><creatorcontrib>Zeng, Hanqing</creatorcontrib><creatorcontrib>Patros, Panagiotis</creatorcontrib><creatorcontrib>Luu, Jason</creatorcontrib><creatorcontrib>Kent, Kenneth B.</creatorcontrib><creatorcontrib>Betz, Vaughn</creatorcontrib><title>VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling</title><title>ACM transactions on reconfigurable technology and systems</title><addtitle>ACM T RECONFIG TECHN</addtitle><description>Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated highquality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3x faster) and memory footprint (3.3x lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools-showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.</description><subject>Computer Science</subject><subject>Computer Science, Hardware &amp; Architecture</subject><subject>Science &amp; Technology</subject><subject>Technology</subject><issn>1936-7406</issn><issn>1936-7414</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>AOWDO</sourceid><recordid>eNqNkNFLwzAQxoMoOKf4L-TNB6kmS5qkvpXqNmGiyPS1pO1li3TNSFJE_3o7NvbswXH38Pu-4z6Erim5o5Sn94wpJag8QSOaMZFITvnpcSfiHF2E8EWIYELxEZp_Lt-xesBzu1onW_DG-Y3uasBF_oh11-CiD9Ft7K-uWsDTt1mOc1-vbYQ69h7wi2ugbW23ukRnRrcBrg5zjD6mT8tinixeZ89FvkhqqmRMMq7oxCiiUyKatJLZ0HpCCKmqRoNsKMtAcaZA8kxMDAeWVUyYhovKsFQxNkY3e9_auxA8mHLr7Ub7n5KSchdAeQhgINWe_IbKmVBbGP460sPJwU5yQXbFCxt1tK4rXN_FQXr7fyn7A_CBa2s</recordid><startdate>20200630</startdate><enddate>20200630</enddate><creator>Murray, Kevin E.</creator><creator>Petelin, Oleg</creator><creator>Zhong, Sheng</creator><creator>Wang, Jia Min</creator><creator>Eldafrawy, Mohamed</creator><creator>Legault, Jean-Philippe</creator><creator>Sha, Eugene</creator><creator>Graham, Aaron G.</creator><creator>Wu, Jean</creator><creator>Walker, Matthew J. P.</creator><creator>Zeng, Hanqing</creator><creator>Patros, Panagiotis</creator><creator>Luu, Jason</creator><creator>Kent, Kenneth B.</creator><creator>Betz, Vaughn</creator><general>Assoc Computing Machinery</general><scope>AOWDO</scope><scope>BLEPL</scope><scope>DTL</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-2578-2147</orcidid><orcidid>https://orcid.org/0000-0002-4157-8584</orcidid><orcidid>https://orcid.org/0000-0003-2764-823X</orcidid><orcidid>https://orcid.org/0000-0002-8535-3432</orcidid><orcidid>https://orcid.org/0000-0002-8151-8359</orcidid></search><sort><creationdate>20200630</creationdate><title>VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling</title><author>Murray, Kevin E. ; Petelin, Oleg ; Zhong, Sheng ; Wang, Jia Min ; Eldafrawy, Mohamed ; Legault, Jean-Philippe ; Sha, Eugene ; Graham, Aaron G. ; Wu, Jean ; Walker, Matthew J. P. ; Zeng, Hanqing ; Patros, Panagiotis ; Luu, Jason ; Kent, Kenneth B. ; Betz, Vaughn</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c187t-94812f80a506d5b795b7a2000bbdae7d139e8438e74962f4e39b36fd46bf35833</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2020</creationdate><topic>Computer Science</topic><topic>Computer Science, Hardware &amp; Architecture</topic><topic>Science &amp; Technology</topic><topic>Technology</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Murray, Kevin E.</creatorcontrib><creatorcontrib>Petelin, Oleg</creatorcontrib><creatorcontrib>Zhong, Sheng</creatorcontrib><creatorcontrib>Wang, Jia Min</creatorcontrib><creatorcontrib>Eldafrawy, Mohamed</creatorcontrib><creatorcontrib>Legault, Jean-Philippe</creatorcontrib><creatorcontrib>Sha, Eugene</creatorcontrib><creatorcontrib>Graham, Aaron G.</creatorcontrib><creatorcontrib>Wu, Jean</creatorcontrib><creatorcontrib>Walker, Matthew J. P.</creatorcontrib><creatorcontrib>Zeng, Hanqing</creatorcontrib><creatorcontrib>Patros, Panagiotis</creatorcontrib><creatorcontrib>Luu, Jason</creatorcontrib><creatorcontrib>Kent, Kenneth B.</creatorcontrib><creatorcontrib>Betz, Vaughn</creatorcontrib><collection>Web of Science - Science Citation Index Expanded - 2020</collection><collection>Web of Science Core Collection</collection><collection>Science Citation Index Expanded</collection><collection>CrossRef</collection><jtitle>ACM transactions on reconfigurable technology and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Murray, Kevin E.</au><au>Petelin, Oleg</au><au>Zhong, Sheng</au><au>Wang, Jia Min</au><au>Eldafrawy, Mohamed</au><au>Legault, Jean-Philippe</au><au>Sha, Eugene</au><au>Graham, Aaron G.</au><au>Wu, Jean</au><au>Walker, Matthew J. P.</au><au>Zeng, Hanqing</au><au>Patros, Panagiotis</au><au>Luu, Jason</au><au>Kent, Kenneth B.</au><au>Betz, Vaughn</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling</atitle><jtitle>ACM transactions on reconfigurable technology and systems</jtitle><stitle>ACM T RECONFIG TECHN</stitle><date>2020-06-30</date><risdate>2020</risdate><volume>13</volume><issue>2</issue><spage>1</spage><epage>55</epage><pages>1-55</pages><artnum>9</artnum><issn>1936-7406</issn><eissn>1936-7414</eissn><abstract>Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated highquality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3x faster) and memory footprint (3.3x lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools-showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.</abstract><cop>NEW YORK</cop><pub>Assoc Computing Machinery</pub><doi>10.1145/3388617</doi><tpages>60</tpages><orcidid>https://orcid.org/0000-0002-2578-2147</orcidid><orcidid>https://orcid.org/0000-0002-4157-8584</orcidid><orcidid>https://orcid.org/0000-0003-2764-823X</orcidid><orcidid>https://orcid.org/0000-0002-8535-3432</orcidid><orcidid>https://orcid.org/0000-0002-8151-8359</orcidid></addata></record>
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subjects Computer Science
Computer Science, Hardware & Architecture
Science & Technology
Technology
title VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-08T04%3A47%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-webofscience_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=VTR%208:%20High-performance%20CAD%20and%20Customizable%20FPGA%20Architecture%20Modelling&rft.jtitle=ACM%20transactions%20on%20reconfigurable%20technology%20and%20systems&rft.au=Murray,%20Kevin%20E.&rft.date=2020-06-30&rft.volume=13&rft.issue=2&rft.spage=1&rft.epage=55&rft.pages=1-55&rft.artnum=9&rft.issn=1936-7406&rft.eissn=1936-7414&rft_id=info:doi/10.1145/3388617&rft_dat=%3Cwebofscience_cross%3E000583746000004%3C/webofscience_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true