Design of a Low Power DSP with Distributed and Early Clock Gating

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word （VLIW） digital signal proces- sor （DSP） was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was...

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Veröffentlicht in:Shanghai jiao tong da xue xue bao 2007-10, Vol.12 (5), p.610-617
1. Verfasser: 王兵 王琴 彭瑞华 付宇卓
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Sprache:eng
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图象分布
时钟机械
逻辑信号处理
逻辑设计
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description A novel clock structure of a low-power 16-bit very large instruction word （VLIW） digital signal proces- sor （DSP） was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch ＆. decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was im- plemented following the Synopsys back-end flow under TSMC （Taiwan Silicon manufacture corporation） 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm × 2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7 % circuit is active simultaneously in average, compared to its non-gating counterparts.
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1995-8188
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subjects 图象分布
时钟机械
逻辑信号处理
逻辑设计
title Design of a Low Power DSP with Distributed and Early Clock Gating
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