记发器信令系统软硬件架构设计改进
为提高传统PSTN电话系统的兼容性及适应性,1号信令系统中的记发器信令部分需要改进硬件电路板相应设计架构,并且针对硬件电路重新设计软件架构.该文针对多路记发器信令接续的需要,设计基于DSP＋ARM＋FPGA的强大性能硬件架构,并提出记发器信令底层部分的软件设计思路及解决方法....
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| Veröffentlicht in: | 科技资讯 2015, Vol.13 (12), p.19-19 |
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| container_title | 科技资讯 |
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| creator | 张小恒 |
| description | 为提高传统PSTN电话系统的兼容性及适应性,1号信令系统中的记发器信令部分需要改进硬件电路板相应设计架构,并且针对硬件电路重新设计软件架构.该文针对多路记发器信令接续的需要,设计基于DSP＋ARM＋FPGA的强大性能硬件架构,并提出记发器信令底层部分的软件设计思路及解决方法. |
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| fulltext | fulltext |
| identifier | ISSN: 1672-3791 |
| ispartof | 科技资讯, 2015, Vol.13 (12), p.19-19 |
| issn | 1672-3791 |
| language | chi |
| recordid | cdi_wanfang_journals_kjzx201512015 |
| source | 国家哲学社会科学学术期刊数据库 (National Social Sciences Database) |
| subjects | armll FPGA 记发器信令 软硬件架构DSP |
| title | 记发器信令系统软硬件架构设计改进 |
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