Semiconductor integrated circuit and electronic device
AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circu...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Otsuga, Kazuo Kanno, Yusuke Takazawa, Yoshio |
description | AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08339190</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08339190</sourcerecordid><originalsourceid>FETCH-uspatents_grants_083391903</originalsourceid><addsrcrecordid>eNrjZDALTs3NTM7PSylNLskvUsjMK0lNL0osSU1RSM4sSi7NLFFIzEtRSM1JTS4pys_LTFZISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqXFBUDdeSXF8UBjQJSBhbGxpaGlgTERSgCsVy7x</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor integrated circuit and electronic device</title><source>USPTO Issued Patents</source><creator>Otsuga, Kazuo ; Kanno, Yusuke ; Takazawa, Yoshio</creator><creatorcontrib>Otsuga, Kazuo ; Kanno, Yusuke ; Takazawa, Yoshio ; Renesas Electronics Corporation</creatorcontrib><description>AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8339190$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8339190$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Otsuga, Kazuo</creatorcontrib><creatorcontrib>Kanno, Yusuke</creatorcontrib><creatorcontrib>Takazawa, Yoshio</creatorcontrib><creatorcontrib>Renesas Electronics Corporation</creatorcontrib><title>Semiconductor integrated circuit and electronic device</title><description>AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDALTs3NTM7PSylNLskvUsjMK0lNL0osSU1RSM4sSi7NLFFIzEtRSM1JTS4pys_LTFZISS3LTE7lYWBNS8wpTuWF0twMCm6uIc4euqXFBUDdeSXF8UBjQJSBhbGxpaGlgTERSgCsVy7x</recordid><startdate>20121225</startdate><enddate>20121225</enddate><creator>Otsuga, Kazuo</creator><creator>Kanno, Yusuke</creator><creator>Takazawa, Yoshio</creator><scope>EFH</scope></search><sort><creationdate>20121225</creationdate><title>Semiconductor integrated circuit and electronic device</title><author>Otsuga, Kazuo ; Kanno, Yusuke ; Takazawa, Yoshio</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_083391903</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Otsuga, Kazuo</creatorcontrib><creatorcontrib>Kanno, Yusuke</creatorcontrib><creatorcontrib>Takazawa, Yoshio</creatorcontrib><creatorcontrib>Renesas Electronics Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Otsuga, Kazuo</au><au>Kanno, Yusuke</au><au>Takazawa, Yoshio</au><aucorp>Renesas Electronics Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor integrated circuit and electronic device</title><date>2012-12-25</date><risdate>2012</risdate><abstract>AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_08339190 |
source | USPTO Issued Patents |
title | Semiconductor integrated circuit and electronic device |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T02%3A02%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Otsuga,%20Kazuo&rft.aucorp=Renesas%20Electronics%20Corporation&rft.date=2012-12-25&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E08339190%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |