Semiconductor device and method of manufacturing the same

Semiconductor device and method of manufacturing the same

In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a su...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kajiwara, Ryoichi, Motowaki, Shigehisa, Ito, Kazutoshi, Ishii, Toshiaki, Arai, Katsuo, Nakajo, Takuya, Kagii, Hidemasa
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Kajiwara, Ryoichi
Motowaki, Shigehisa
Ito, Kazutoshi
Ishii, Toshiaki
Arai, Katsuo
Nakajo, Takuya
Kagii, Hidemasa
description In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08314484</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08314484</sourcerecordid><originalsourceid>FETCH-uspatents_grants_083144843</originalsourceid><addsrcrecordid>eNrjZLAMTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUchPU8hNzCtNS0wuKS3KzEtXKMlIVShOzE3lYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDC2NDExMLEmAglABttL6E</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and method of manufacturing the same</title><source>USPTO Issued Patents</source><creator>Kajiwara, Ryoichi ; Motowaki, Shigehisa ; Ito, Kazutoshi ; Ishii, Toshiaki ; Arai, Katsuo ; Nakajo, Takuya ; Kagii, Hidemasa</creator><creatorcontrib>Kajiwara, Ryoichi ; Motowaki, Shigehisa ; Ito, Kazutoshi ; Ishii, Toshiaki ; Arai, Katsuo ; Nakajo, Takuya ; Kagii, Hidemasa ; Renesas Electronics Corporation</creatorcontrib><description>In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8314484$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8314484$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kajiwara, Ryoichi</creatorcontrib><creatorcontrib>Motowaki, Shigehisa</creatorcontrib><creatorcontrib>Ito, Kazutoshi</creatorcontrib><creatorcontrib>Ishii, Toshiaki</creatorcontrib><creatorcontrib>Arai, Katsuo</creatorcontrib><creatorcontrib>Nakajo, Takuya</creatorcontrib><creatorcontrib>Kagii, Hidemasa</creatorcontrib><creatorcontrib>Renesas Electronics Corporation</creatorcontrib><title>Semiconductor device and method of manufacturing the same</title><description>In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLAMTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE0tychPUchPU8hNzCtNS0wuKS3KzEtXKMlIVShOzE3lYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDC2NDExMLEmAglABttL6E</recordid><startdate>20121120</startdate><enddate>20121120</enddate><creator>Kajiwara, Ryoichi</creator><creator>Motowaki, Shigehisa</creator><creator>Ito, Kazutoshi</creator><creator>Ishii, Toshiaki</creator><creator>Arai, Katsuo</creator><creator>Nakajo, Takuya</creator><creator>Kagii, Hidemasa</creator><scope>EFH</scope></search><sort><creationdate>20121120</creationdate><title>Semiconductor device and method of manufacturing the same</title><author>Kajiwara, Ryoichi ; Motowaki, Shigehisa ; Ito, Kazutoshi ; Ishii, Toshiaki ; Arai, Katsuo ; Nakajo, Takuya ; Kagii, Hidemasa</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_083144843</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kajiwara, Ryoichi</creatorcontrib><creatorcontrib>Motowaki, Shigehisa</creatorcontrib><creatorcontrib>Ito, Kazutoshi</creatorcontrib><creatorcontrib>Ishii, Toshiaki</creatorcontrib><creatorcontrib>Arai, Katsuo</creatorcontrib><creatorcontrib>Nakajo, Takuya</creatorcontrib><creatorcontrib>Kagii, Hidemasa</creatorcontrib><creatorcontrib>Renesas Electronics Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kajiwara, Ryoichi</au><au>Motowaki, Shigehisa</au><au>Ito, Kazutoshi</au><au>Ishii, Toshiaki</au><au>Arai, Katsuo</au><au>Nakajo, Takuya</au><au>Kagii, Hidemasa</au><aucorp>Renesas Electronics Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and method of manufacturing the same</title><date>2012-11-20</date><risdate>2012</risdate><abstract>In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_08314484
source USPTO Issued Patents
title Semiconductor device and method of manufacturing the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T15%3A03%3A12IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kajiwara,%20Ryoichi&rft.aucorp=Renesas%20Electronics%20Corporation&rft.date=2012-11-20&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E08314484%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true