Multiple die stack package
A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.
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| creator | Khiang, Wang Chuen Chuan, Koh Yong Chin, Fong Kok |
| description | A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08288862</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08288862</sourcerecordid><originalsourceid>FETCH-uspatents_grants_082888623</originalsourceid><addsrcrecordid>eNrjZJDyLc0pySzISVVIyUxVKC5JTM5WKAASiempPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBlYGFlYWJgZGROhBAAcjiPD</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multiple die stack package</title><source>USPTO Issued Patents</source><creator>Khiang, Wang Chuen ; Chuan, Koh Yong ; Chin, Fong Kok</creator><creatorcontrib>Khiang, Wang Chuen ; Chuan, Koh Yong ; Chin, Fong Kok ; United Test & Assembly Center Limited</creatorcontrib><description>A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8288862$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8288862$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Khiang, Wang Chuen</creatorcontrib><creatorcontrib>Chuan, Koh Yong</creatorcontrib><creatorcontrib>Chin, Fong Kok</creatorcontrib><creatorcontrib>United Test & Assembly Center Limited</creatorcontrib><title>Multiple die stack package</title><description>A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZJDyLc0pySzISVVIyUxVKC5JTM5WKAASiempPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBlYGFlYWJgZGROhBAAcjiPD</recordid><startdate>20121016</startdate><enddate>20121016</enddate><creator>Khiang, Wang Chuen</creator><creator>Chuan, Koh Yong</creator><creator>Chin, Fong Kok</creator><scope>EFH</scope></search><sort><creationdate>20121016</creationdate><title>Multiple die stack package</title><author>Khiang, Wang Chuen ; Chuan, Koh Yong ; Chin, Fong Kok</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_082888623</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Khiang, Wang Chuen</creatorcontrib><creatorcontrib>Chuan, Koh Yong</creatorcontrib><creatorcontrib>Chin, Fong Kok</creatorcontrib><creatorcontrib>United Test & Assembly Center Limited</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Khiang, Wang Chuen</au><au>Chuan, Koh Yong</au><au>Chin, Fong Kok</au><aucorp>United Test & Assembly Center Limited</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multiple die stack package</title><date>2012-10-16</date><risdate>2012</risdate><abstract>A semiconductor package, containing two or more stacked IC devices attached to a substrate. Each of the IC devices has a plurality of electrical contact regions which are connected to the substrate by means of electrical connections.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
| recordid | cdi_uspatents_grants_08288862 |
| source | USPTO Issued Patents |
| title | Multiple die stack package |
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