Overlay vernier key and method for fabricating the same

Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of t...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Cho, Byeong Ho, Ko, Sung Woo
Format: Patent
Sprache:eng
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