Method to attain low defectivity fully silicided gates
A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A bl...
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creator | Visokay, Mark Robert Mehrad, Freidoon Guldi, Richard L Obeng, Yaw Samuel |
description | A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes. |
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The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. 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The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDDzTS3JyE9RKMlXSCwpSczMU8jJL1dISU1LTS7JLMssqVRIK83JqVQozszJTM5MSU1RSE8sSS3mYWBNS8wpTuWF0twMCm6uIc4euqXFBUD5vJLi-PSiRBBlYGFkbmxmYmpMhBIAdPUukg</recordid><startdate>20120925</startdate><enddate>20120925</enddate><creator>Visokay, Mark Robert</creator><creator>Mehrad, Freidoon</creator><creator>Guldi, Richard L</creator><creator>Obeng, Yaw Samuel</creator><scope>EFH</scope></search><sort><creationdate>20120925</creationdate><title>Method to attain low defectivity fully silicided gates</title><author>Visokay, Mark Robert ; Mehrad, Freidoon ; Guldi, Richard L ; Obeng, Yaw Samuel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_082736453</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Visokay, Mark Robert</creatorcontrib><creatorcontrib>Mehrad, Freidoon</creatorcontrib><creatorcontrib>Guldi, Richard L</creatorcontrib><creatorcontrib>Obeng, Yaw Samuel</creatorcontrib><creatorcontrib>Texas Instruments Incorporated</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Visokay, Mark Robert</au><au>Mehrad, Freidoon</au><au>Guldi, Richard L</au><au>Obeng, Yaw Samuel</au><aucorp>Texas Instruments Incorporated</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method to attain low defectivity fully silicided gates</title><date>2012-09-25</date><risdate>2012</risdate><abstract>A method of forming fully silicided (FUSI) gates in MOS transistors which is compatible with wet etch processes used in source/drain silicide formation is disclosed. The gate silicide formation step produces a top layer of metal rich silicide which is resistant to removal in wet etch processes. A blocking layer over active areas prevents source/drain silicide formation during gate silicide formation. Wet etches during removal of the blocking layer and source/drain metal strip do not remove the metal rich gate silicide layer. Anneal of the gate silicide to produce a FUSI gate with a desired stoichiometry is delayed until after formation of the source/drain silicide. The disclosed method is compatible with nickel and nickel-platinum silicide processes.</abstract><oa>free_for_read</oa></addata></record> |
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title | Method to attain low defectivity fully silicided gates |
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