Dual-damascene process to fabricate thick wire structure

A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop la...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Coolbaugh, Douglas D, Downes, Keith E, Lindgren, Peter J, Stamper, Anthony K
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Coolbaugh, Douglas D
Downes, Keith E
Lindgren, Peter J
Stamper, Anthony K
description A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08236663</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08236663</sourcerecordid><originalsourceid>FETCH-uspatents_grants_082366633</originalsourceid><addsrcrecordid>eNrjZLBwKU3M0U1JzE0sTk7NS1UoKMpPTi0uVijJV0hLTCrKTE4sSVUoychMzlYozyxKVSguKSpNLiktSuVhYE1LzClO5YXS3AwKbq4hzh66pcUFQD15JcXx6UWJIMrAwsjYzMzM2JgIJQDkUS9j</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dual-damascene process to fabricate thick wire structure</title><source>USPTO Issued Patents</source><creator>Coolbaugh, Douglas D ; Downes, Keith E ; Lindgren, Peter J ; Stamper, Anthony K</creator><creatorcontrib>Coolbaugh, Douglas D ; Downes, Keith E ; Lindgren, Peter J ; Stamper, Anthony K ; International Business Machines Corporation</creatorcontrib><description>A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8236663$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,309,781,803,886,64044</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8236663$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Coolbaugh, Douglas D</creatorcontrib><creatorcontrib>Downes, Keith E</creatorcontrib><creatorcontrib>Lindgren, Peter J</creatorcontrib><creatorcontrib>Stamper, Anthony K</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Dual-damascene process to fabricate thick wire structure</title><description>A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLBwKU3M0U1JzE0sTk7NS1UoKMpPTi0uVijJV0hLTCrKTE4sSVUoychMzlYozyxKVSguKSpNLiktSuVhYE1LzClO5YXS3AwKbq4hzh66pcUFQD15JcXx6UWJIMrAwsjYzMzM2JgIJQDkUS9j</recordid><startdate>20120807</startdate><enddate>20120807</enddate><creator>Coolbaugh, Douglas D</creator><creator>Downes, Keith E</creator><creator>Lindgren, Peter J</creator><creator>Stamper, Anthony K</creator><scope>EFH</scope></search><sort><creationdate>20120807</creationdate><title>Dual-damascene process to fabricate thick wire structure</title><author>Coolbaugh, Douglas D ; Downes, Keith E ; Lindgren, Peter J ; Stamper, Anthony K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_082366633</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Coolbaugh, Douglas D</creatorcontrib><creatorcontrib>Downes, Keith E</creatorcontrib><creatorcontrib>Lindgren, Peter J</creatorcontrib><creatorcontrib>Stamper, Anthony K</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Coolbaugh, Douglas D</au><au>Downes, Keith E</au><au>Lindgren, Peter J</au><au>Stamper, Anthony K</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dual-damascene process to fabricate thick wire structure</title><date>2012-08-07</date><risdate>2012</risdate><abstract>A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_08236663
source USPTO Issued Patents
title Dual-damascene process to fabricate thick wire structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-14T17%3A32%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Coolbaugh,%20Douglas%20D&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2012-08-07&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E08236663%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true