System for vertical DMOS with slots
A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within...
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creator | Alter, Martin Husher, John Durbin |
description | A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies. |
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fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08227860</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08227860</sourcerecordid><originalsourceid>FETCH-uspatents_grants_082278603</originalsourceid><addsrcrecordid>eNrjZFAOriwuSc1VSMsvUihLLSrJTE7MUXDx9Q9WKM8syVAozskvKeZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwMLIyNzCzMCYCCUAldYm5A</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System for vertical DMOS with slots</title><source>USPTO Issued Patents</source><creator>Alter, Martin ; Husher, John Durbin</creator><creatorcontrib>Alter, Martin ; Husher, John Durbin ; Micrel, Inc</creatorcontrib><description>A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8227860$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8227860$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Alter, Martin</creatorcontrib><creatorcontrib>Husher, John Durbin</creatorcontrib><creatorcontrib>Micrel, Inc</creatorcontrib><title>System for vertical DMOS with slots</title><description>A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZFAOriwuSc1VSMsvUihLLSrJTE7MUXDx9Q9WKM8syVAozskvKeZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwMLIyNzCzMCYCCUAldYm5A</recordid><startdate>20120724</startdate><enddate>20120724</enddate><creator>Alter, Martin</creator><creator>Husher, John Durbin</creator><scope>EFH</scope></search><sort><creationdate>20120724</creationdate><title>System for vertical DMOS with slots</title><author>Alter, Martin ; Husher, John Durbin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_082278603</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Alter, Martin</creatorcontrib><creatorcontrib>Husher, John Durbin</creatorcontrib><creatorcontrib>Micrel, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Alter, Martin</au><au>Husher, John Durbin</au><aucorp>Micrel, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System for vertical DMOS with slots</title><date>2012-07-24</date><risdate>2012</risdate><abstract>A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.</abstract><oa>free_for_read</oa></addata></record> |
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title | System for vertical DMOS with slots |
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