Method and apparatus for implementing processor instructions for accelerating public-key cryptography

In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a...

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Hauptverfasser:	Shantz, Sheueling Chang, Rarick, Leonard, Spracklen, Lawrence, Eberle, Hans, Gura, Nils
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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