Memory interface including an efficient variable-width bus

A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.