Interactive design optimization techniques and interface

Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be o...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Milton, David Ian M
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Milton, David Ian M
description Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be overlaid on top of a floorplan layout of the IC to highlight the parts of the design that may be further optimized. The visual indicator can be updated in real time to highlight the optimizations that have been achieved by the changes made to the design. The real time update of the visual indicator may allow multiple changes to be made to the design before the design is recompiled with a design program.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08196085</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08196085</sourcerecordid><originalsourceid>FETCH-uspatents_grants_081960853</originalsourceid><addsrcrecordid>eNrjZLDwzCtJLUpMLsksS1VISS3OTM9TyC8oyczNrEosyczPUyhJTc7IyywsTS1WSMxLUcgEKU9LTE7lYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDC0NLMwMLUmAglAC9fL_M</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Interactive design optimization techniques and interface</title><source>USPTO Issued Patents</source><creator>Milton, David Ian M</creator><creatorcontrib>Milton, David Ian M ; Altera Corporation</creatorcontrib><description>Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be overlaid on top of a floorplan layout of the IC to highlight the parts of the design that may be further optimized. The visual indicator can be updated in real time to highlight the optimizations that have been achieved by the changes made to the design. The real time update of the visual indicator may allow multiple changes to be made to the design before the design is recompiled with a design program.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8196085$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64015</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8196085$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Milton, David Ian M</creatorcontrib><creatorcontrib>Altera Corporation</creatorcontrib><title>Interactive design optimization techniques and interface</title><description>Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be overlaid on top of a floorplan layout of the IC to highlight the parts of the design that may be further optimized. The visual indicator can be updated in real time to highlight the optimizations that have been achieved by the changes made to the design. The real time update of the visual indicator may allow multiple changes to be made to the design before the design is recompiled with a design program.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLDwzCtJLUpMLsksS1VISS3OTM9TyC8oyczNrEosyczPUyhJTc7IyywsTS1WSMxLUcgEKU9LTE7lYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDC0NLMwMLUmAglAC9fL_M</recordid><startdate>20120605</startdate><enddate>20120605</enddate><creator>Milton, David Ian M</creator><scope>EFH</scope></search><sort><creationdate>20120605</creationdate><title>Interactive design optimization techniques and interface</title><author>Milton, David Ian M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_081960853</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Milton, David Ian M</creatorcontrib><creatorcontrib>Altera Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Milton, David Ian M</au><aucorp>Altera Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Interactive design optimization techniques and interface</title><date>2012-06-05</date><risdate>2012</risdate><abstract>Techniques for analyzing and optimizing a design on an integrated circuit (IC) are provided. The techniques include an interface that aids interactive optimization. A visual indicator is generated based on the power usage value of each of the logic blocks in the design. The visual indicator can be overlaid on top of a floorplan layout of the IC to highlight the parts of the design that may be further optimized. The visual indicator can be updated in real time to highlight the optimizations that have been achieved by the changes made to the design. The real time update of the visual indicator may allow multiple changes to be made to the design before the design is recompiled with a design program.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_08196085
source USPTO Issued Patents
title Interactive design optimization techniques and interface
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T17%3A52%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Milton,%20David%20Ian%20M&rft.aucorp=Altera%20Corporation&rft.date=2012-06-05&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E08196085%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true