Automated processor generation system and method for designing a configurable processor
A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor stat...
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creator | Wang, Albert Ren-Rui Ruddell, Richard Goodwin, David William Killian, Earl A Bhattacharyya, Nupur Medina, Marines Puig Lichtenstein, Walter David Konas, Pavlos Srinivasan, Rangarajan Songer, Christopher Mark Parameswar, Akilesh Maydan, Dror E Gonzalez, Ricardo E |
description | A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. |
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fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08161432</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08161432</sourcerecordid><originalsourceid>FETCH-uspatents_grants_081614323</originalsourceid><addsrcrecordid>eNqNjTEKAjEQANNYiPqH_YDgeSK2hyg-QLCU9bKJgcvukd0U_t4TBFuraYaZubt11SSjkYexSE-qUiASU0FLwqAvNcqA7CGTPcVDmARPmiInjoDQC4cUa8HHQL_G0s0CDkqrLxcOzqfr8bKuOk43Nr3Hgh9sDs2-2bXb9g_lDYHoO5g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Automated processor generation system and method for designing a configurable processor</title><source>USPTO Issued Patents</source><creator>Wang, Albert Ren-Rui ; Ruddell, Richard ; Goodwin, David William ; Killian, Earl A ; Bhattacharyya, Nupur ; Medina, Marines Puig ; Lichtenstein, Walter David ; Konas, Pavlos ; Srinivasan, Rangarajan ; Songer, Christopher Mark ; Parameswar, Akilesh ; Maydan, Dror E ; Gonzalez, Ricardo E</creator><creatorcontrib>Wang, Albert Ren-Rui ; Ruddell, Richard ; Goodwin, David William ; Killian, Earl A ; Bhattacharyya, Nupur ; Medina, Marines Puig ; Lichtenstein, Walter David ; Konas, Pavlos ; Srinivasan, Rangarajan ; Songer, Christopher Mark ; Parameswar, Akilesh ; Maydan, Dror E ; Gonzalez, Ricardo E ; Tensilica, Inc</creatorcontrib><description>A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.</description><language>eng</language><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8161432$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,309,781,803,886,64044</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8161432$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Wang, Albert Ren-Rui</creatorcontrib><creatorcontrib>Ruddell, Richard</creatorcontrib><creatorcontrib>Goodwin, David William</creatorcontrib><creatorcontrib>Killian, Earl A</creatorcontrib><creatorcontrib>Bhattacharyya, Nupur</creatorcontrib><creatorcontrib>Medina, Marines Puig</creatorcontrib><creatorcontrib>Lichtenstein, Walter David</creatorcontrib><creatorcontrib>Konas, Pavlos</creatorcontrib><creatorcontrib>Srinivasan, Rangarajan</creatorcontrib><creatorcontrib>Songer, Christopher Mark</creatorcontrib><creatorcontrib>Parameswar, Akilesh</creatorcontrib><creatorcontrib>Maydan, Dror E</creatorcontrib><creatorcontrib>Gonzalez, Ricardo E</creatorcontrib><creatorcontrib>Tensilica, Inc</creatorcontrib><title>Automated processor generation system and method for designing a configurable processor</title><description>A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjTEKAjEQANNYiPqH_YDgeSK2hyg-QLCU9bKJgcvukd0U_t4TBFuraYaZubt11SSjkYexSE-qUiASU0FLwqAvNcqA7CGTPcVDmARPmiInjoDQC4cUa8HHQL_G0s0CDkqrLxcOzqfr8bKuOk43Nr3Hgh9sDs2-2bXb9g_lDYHoO5g</recordid><startdate>20120417</startdate><enddate>20120417</enddate><creator>Wang, Albert Ren-Rui</creator><creator>Ruddell, Richard</creator><creator>Goodwin, David William</creator><creator>Killian, Earl A</creator><creator>Bhattacharyya, Nupur</creator><creator>Medina, Marines Puig</creator><creator>Lichtenstein, Walter David</creator><creator>Konas, Pavlos</creator><creator>Srinivasan, Rangarajan</creator><creator>Songer, Christopher Mark</creator><creator>Parameswar, Akilesh</creator><creator>Maydan, Dror E</creator><creator>Gonzalez, Ricardo E</creator><scope>EFH</scope></search><sort><creationdate>20120417</creationdate><title>Automated processor generation system and method for designing a configurable processor</title><author>Wang, Albert Ren-Rui ; Ruddell, Richard ; Goodwin, David William ; Killian, Earl A ; Bhattacharyya, Nupur ; Medina, Marines Puig ; Lichtenstein, Walter David ; Konas, Pavlos ; Srinivasan, Rangarajan ; Songer, Christopher Mark ; Parameswar, Akilesh ; Maydan, Dror E ; Gonzalez, Ricardo E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_081614323</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Wang, Albert Ren-Rui</creatorcontrib><creatorcontrib>Ruddell, Richard</creatorcontrib><creatorcontrib>Goodwin, David William</creatorcontrib><creatorcontrib>Killian, Earl A</creatorcontrib><creatorcontrib>Bhattacharyya, Nupur</creatorcontrib><creatorcontrib>Medina, Marines Puig</creatorcontrib><creatorcontrib>Lichtenstein, Walter David</creatorcontrib><creatorcontrib>Konas, Pavlos</creatorcontrib><creatorcontrib>Srinivasan, Rangarajan</creatorcontrib><creatorcontrib>Songer, Christopher Mark</creatorcontrib><creatorcontrib>Parameswar, Akilesh</creatorcontrib><creatorcontrib>Maydan, Dror E</creatorcontrib><creatorcontrib>Gonzalez, Ricardo E</creatorcontrib><creatorcontrib>Tensilica, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wang, Albert Ren-Rui</au><au>Ruddell, Richard</au><au>Goodwin, David William</au><au>Killian, Earl A</au><au>Bhattacharyya, Nupur</au><au>Medina, Marines Puig</au><au>Lichtenstein, Walter David</au><au>Konas, Pavlos</au><au>Srinivasan, Rangarajan</au><au>Songer, Christopher Mark</au><au>Parameswar, Akilesh</au><au>Maydan, Dror E</au><au>Gonzalez, Ricardo E</au><aucorp>Tensilica, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Automated processor generation system and method for designing a configurable processor</title><date>2012-04-17</date><risdate>2012</risdate><abstract>A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.</abstract><oa>free_for_read</oa></addata></record> |
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title | Automated processor generation system and method for designing a configurable processor |
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