Low resistance integrated MOS structure

The present invention is related to a metal-oxide semiconductor field-effect transistor (MOSFET) having a symmetrical layout such that the resistance between drains and sources is reduced, thereby reducing power dissipation. Drain pads, source pads, and gates are placed on the MOSFET such that the d...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Pierrel, Maud, Manai, Bilal
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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