Fast Fourier transformation circuit

Provided is a fast Fourier transformation circuit capable of optimizing an operation resource while matching a plurality of communication systems. In this circuit, an FFT circuit comprises a first FFT operation unit for subjecting two-parallel 2 digital signals to FFT operations of (M−1) steps, a second FFT operation unit for subjecting 2 digital signals to FFT operations of (N−M+) steps, and a third FFT operation unit for subjecting 2 digital signals to an FFT operation of one step. The output signal of the first FFT operation unit is subjected to the FFT operation by the second FFT operation unit and the third FFT operation unit thereby to perform the FFT operations of 2 points and 2 points simultaneously.