Method of programming an array of NMOS EEPROM cells that minimizes bit disturbances and voltage withstand requirements for the memory array and supporting circuits

A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated...

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Bibliographische Detailangaben

Hauptverfasser:	Shields, Jeffrey A, Hewitt, Kent D, Gerber, Donald S
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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