Pixel structure, thin film transistor array substrate, display panel, and display apparatus with particular parasitic capacitance compensation

A pixel structure adapts for compensating variation of gate-drain parasitic capacitance caused by misalignment in manufacturing process by forming a transverse compensation capacitance between a capacitance compensation portion and a scan line in an in-plane direction, and therefore the flicker in displaying of a display panel can be alleviated. In addition, being applied into a concept of "data lines reducing", the pixel structure is capable of reducing difference of capacitance between two adjacent pixel structures due to misalignment in manufacturing process and improving display uniformity. Furthermore, a thin film transistor array substrate, a display panel, and a display apparatus applying the pixel structure are also provided.