Two-phase clock-stalling technique for error detection and error correction

One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagat...

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Bibliographische Detailangaben

Hauptverfasser:	Dartu, Florentin, Shenoy, Narendra V
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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