System and methodology for determining layout-dependent effects in ULSI simulation

System and methodology for determining layout-dependent effects in ULSI simulation

A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithograp...

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Hauptverfasser: Chidambarrao, Dureseti, Li, Tong, Williams, Richard Q, Winston, David W
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Sprache:eng
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creator Chidambarrao, Dureseti
Li, Tong
Williams, Richard Q
Winston, David W
description A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08037433</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08037433</sourcerecordid><originalsourceid>FETCH-uspatents_grants_080374333</originalsourceid><addsrcrecordid>eNqNyzEKAjEQQNFtLES9w1xgYSGC9uKiYOVqLYOZxEAysySTIrdXwQNYveb_ZXedWlFKgGwhkb7EShTfwEkGS0o5BQ7sIWKTqr2lmdgSK5Bz9NQCgeF-mc5QQqoRNQivu4XDWGjzc9XBeLwdTn0tM-rnLQ-f8cuwH8xua4z5I3kDAzI5Og</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>System and methodology for determining layout-dependent effects in ULSI simulation</title><source>USPTO Issued Patents</source><creator>Chidambarrao, Dureseti ; Li, Tong ; Williams, Richard Q ; Winston, David W</creator><creatorcontrib>Chidambarrao, Dureseti ; Li, Tong ; Williams, Richard Q ; Winston, David W ; International Business Machines Corporation</creatorcontrib><description>A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.</description><language>eng</language><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8037433$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8037433$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chidambarrao, Dureseti</creatorcontrib><creatorcontrib>Li, Tong</creatorcontrib><creatorcontrib>Williams, Richard Q</creatorcontrib><creatorcontrib>Winston, David W</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>System and methodology for determining layout-dependent effects in ULSI simulation</title><description>A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNyzEKAjEQQNFtLES9w1xgYSGC9uKiYOVqLYOZxEAysySTIrdXwQNYveb_ZXedWlFKgGwhkb7EShTfwEkGS0o5BQ7sIWKTqr2lmdgSK5Bz9NQCgeF-mc5QQqoRNQivu4XDWGjzc9XBeLwdTn0tM-rnLQ-f8cuwH8xua4z5I3kDAzI5Og</recordid><startdate>20111011</startdate><enddate>20111011</enddate><creator>Chidambarrao, Dureseti</creator><creator>Li, Tong</creator><creator>Williams, Richard Q</creator><creator>Winston, David W</creator><scope>EFH</scope></search><sort><creationdate>20111011</creationdate><title>System and methodology for determining layout-dependent effects in ULSI simulation</title><author>Chidambarrao, Dureseti ; Li, Tong ; Williams, Richard Q ; Winston, David W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_080374333</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Chidambarrao, Dureseti</creatorcontrib><creatorcontrib>Li, Tong</creatorcontrib><creatorcontrib>Williams, Richard Q</creatorcontrib><creatorcontrib>Winston, David W</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chidambarrao, Dureseti</au><au>Li, Tong</au><au>Williams, Richard Q</au><au>Winston, David W</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System and methodology for determining layout-dependent effects in ULSI simulation</title><date>2011-10-11</date><risdate>2011</risdate><abstract>A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.</abstract><oa>free_for_read</oa></addata></record>
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title System and methodology for determining layout-dependent effects in ULSI simulation
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T17%3A54%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chidambarrao,%20Dureseti&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2011-10-11&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E08037433%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true