Generation of trace elements within a data processing apparatus
A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Williams, Michael John Ashfield, Edmond John Simon Horley, John Michael |
description | A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation. A trace analysing apparatus can then be provided to reconstruct such omitted information based on a tracked architectural state value of the relevant item of architectural state. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_08037363</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>08037363</sourcerecordid><originalsourceid>FETCH-uspatents_grants_080373633</originalsourceid><addsrcrecordid>eNrjZLB3T81LLUosyczPU8hPUygpSkxOVUjNSc1NzSspVijPLMnIzFNIVEhJLElUKCjKT04tLs7MS1dILChIBOoqLeZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSUgQ-LTixJBlIGFgbG5sZmxMRFKAGZHMfk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Generation of trace elements within a data processing apparatus</title><source>USPTO Issued Patents</source><creator>Williams, Michael John ; Ashfield, Edmond John Simon ; Horley, John Michael</creator><creatorcontrib>Williams, Michael John ; Ashfield, Edmond John Simon ; Horley, John Michael ; ARM Limited</creatorcontrib><description>A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation. A trace analysing apparatus can then be provided to reconstruct such omitted information based on a tracked architectural state value of the relevant item of architectural state.</description><language>eng</language><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8037363$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,778,800,883,64020</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/8037363$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Williams, Michael John</creatorcontrib><creatorcontrib>Ashfield, Edmond John Simon</creatorcontrib><creatorcontrib>Horley, John Michael</creatorcontrib><creatorcontrib>ARM Limited</creatorcontrib><title>Generation of trace elements within a data processing apparatus</title><description>A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation. A trace analysing apparatus can then be provided to reconstruct such omitted information based on a tracked architectural state value of the relevant item of architectural state.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZLB3T81LLUosyczPU8hPUygpSkxOVUjNSc1NzSspVijPLMnIzFNIVEhJLElUKCjKT04tLs7MS1dILChIBOoqLeZhYE1LzClO5YXS3AwKbq4hzh66pcUFiSUgQ-LTixJBlIGFgbG5sZmxMRFKAGZHMfk</recordid><startdate>20111011</startdate><enddate>20111011</enddate><creator>Williams, Michael John</creator><creator>Ashfield, Edmond John Simon</creator><creator>Horley, John Michael</creator><scope>EFH</scope></search><sort><creationdate>20111011</creationdate><title>Generation of trace elements within a data processing apparatus</title><author>Williams, Michael John ; Ashfield, Edmond John Simon ; Horley, John Michael</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_080373633</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Williams, Michael John</creatorcontrib><creatorcontrib>Ashfield, Edmond John Simon</creatorcontrib><creatorcontrib>Horley, John Michael</creatorcontrib><creatorcontrib>ARM Limited</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Williams, Michael John</au><au>Ashfield, Edmond John Simon</au><au>Horley, John Michael</au><aucorp>ARM Limited</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Generation of trace elements within a data processing apparatus</title><date>2011-10-11</date><risdate>2011</risdate><abstract>A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation. A trace analysing apparatus can then be provided to reconstruct such omitted information based on a tracked architectural state value of the relevant item of architectural state.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_08037363 |
source | USPTO Issued Patents |
title | Generation of trace elements within a data processing apparatus |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T17%3A20%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Williams,%20Michael%20John&rft.aucorp=ARM%20Limited&rft.date=2011-10-11&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E08037363%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |