Random initialization of latches in an integrated circuit design for simulation

Latches in a net of a simulated integrated circuit design are initialized to known logical states prior to application of a reset signal at the beginning of the simulation. The logical states may be set by generating a list of the latches, sorting them in random order, and then dividing them into tw...

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Bibliographische Detailangaben

Hauptverfasser:	Hira, Kalpesh, Panchal, Neil A
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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