On-chip scan clock generator for ASIC testing
A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence o...
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| creator | Clark, Iain Dirks, Juergen |
| description | A scan clock generator includes a clock signal input for receiving a clock signal, a scan shift mode signal input for receiving a scan shift mode signal, and a sequence controller coupled to the clock signal input for gating a selected number of clock signal pulses at a time to generate a sequence of nonconcurrent scan clock signals at separate outputs respectively in response to a first state of the scan shift mode signal. |
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| source | USPTO Issued Patents |
| title | On-chip scan clock generator for ASIC testing |
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