Low leakage and data retention circuitry

Low leakage and data retention circuitry

An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Hoberman, Barry A, Hillman, Daniel L, Walker, William G, Callahan, John M, Zampaglione, Michael A, Cole, Andrew
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Hoberman, Barry A
Hillman, Daniel L
Walker, William G
Callahan, John M
Zampaglione, Michael A
Cole, Andrew
description An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07940081</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07940081</sourcerecordid><originalsourceid>FETCH-uspatents_grants_079400813</originalsourceid><addsrcrecordid>eNrjZNDwyS9XyElNzE5MT1VIzEtRSEksSVQoSi1JzSvJzM9TSM4sSi7NLCmq5GFgTUvMKU7lhdLcDApuriHOHrqlxQWJINXF8elFiSDKwNzSxMDAwtCYCCUAl3QpFg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Low leakage and data retention circuitry</title><source>USPTO Issued Patents</source><creator>Hoberman, Barry A ; Hillman, Daniel L ; Walker, William G ; Callahan, John M ; Zampaglione, Michael A ; Cole, Andrew</creator><creatorcontrib>Hoberman, Barry A ; Hillman, Daniel L ; Walker, William G ; Callahan, John M ; Zampaglione, Michael A ; Cole, Andrew ; MOSAID Technologies Incorporated</creatorcontrib><description>An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.</description><language>eng</language><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7940081$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7940081$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hoberman, Barry A</creatorcontrib><creatorcontrib>Hillman, Daniel L</creatorcontrib><creatorcontrib>Walker, William G</creatorcontrib><creatorcontrib>Callahan, John M</creatorcontrib><creatorcontrib>Zampaglione, Michael A</creatorcontrib><creatorcontrib>Cole, Andrew</creatorcontrib><creatorcontrib>MOSAID Technologies Incorporated</creatorcontrib><title>Low leakage and data retention circuitry</title><description>An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZNDwyS9XyElNzE5MT1VIzEtRSEksSVQoSi1JzSvJzM9TSM4sSi7NLCmq5GFgTUvMKU7lhdLcDApuriHOHrqlxQWJINXF8elFiSDKwNzSxMDAwtCYCCUAl3QpFg</recordid><startdate>20110510</startdate><enddate>20110510</enddate><creator>Hoberman, Barry A</creator><creator>Hillman, Daniel L</creator><creator>Walker, William G</creator><creator>Callahan, John M</creator><creator>Zampaglione, Michael A</creator><creator>Cole, Andrew</creator><scope>EFH</scope></search><sort><creationdate>20110510</creationdate><title>Low leakage and data retention circuitry</title><author>Hoberman, Barry A ; Hillman, Daniel L ; Walker, William G ; Callahan, John M ; Zampaglione, Michael A ; Cole, Andrew</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_079400813</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Hoberman, Barry A</creatorcontrib><creatorcontrib>Hillman, Daniel L</creatorcontrib><creatorcontrib>Walker, William G</creatorcontrib><creatorcontrib>Callahan, John M</creatorcontrib><creatorcontrib>Zampaglione, Michael A</creatorcontrib><creatorcontrib>Cole, Andrew</creatorcontrib><creatorcontrib>MOSAID Technologies Incorporated</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hoberman, Barry A</au><au>Hillman, Daniel L</au><au>Walker, William G</au><au>Callahan, John M</au><au>Zampaglione, Michael A</au><au>Cole, Andrew</au><aucorp>MOSAID Technologies Incorporated</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Low leakage and data retention circuitry</title><date>2011-05-10</date><risdate>2011</risdate><abstract>An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07940081
source USPTO Issued Patents
title Low leakage and data retention circuitry
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T18%3A55%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Hoberman,%20Barry%20A&rft.aucorp=MOSAID%20Technologies%20Incorporated&rft.date=2011-05-10&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07940081%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true