Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state

Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state

A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruen...

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Hauptverfasser: Irish, John David, McBride, Chad B, Randolph, Jack Chris
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Sprache:eng
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creator Irish, John David
McBride, Chad B
Randolph, Jack Chris
description A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.
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When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use.</abstract><oa>free_for_read</oa></addata></record>
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title Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state
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