Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector
The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surfa...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Chu, Jack O Dehlinger, Gabriel K Grill, Alfred Koester, Steven J Ouyang, Qiqing Schaub, Jeremy D |
description | The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07915653</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07915653</sourcerecordid><originalsourceid>FETCH-uspatents_grants_079156533</originalsourceid><addsrcrecordid>eNqNjE0KwjAQhbtxIeod5gIBpVRxXfzZiIu6l2kyaQJtJiST-xvBA7j6eLzvvXUzDpKKlpIILCfAYGAhcWyALVgck9coPkyA4PzkVI5EBvrHc1Cal1i7cSa4keKgfMhlRqk30bGwISFd07ZZWZwz7X7cNHC9vPq7KrnuKUh-Twm_2J_Oh-7Yte0fyge7Nj6g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector</title><source>USPTO Issued Patents</source><creator>Chu, Jack O ; Dehlinger, Gabriel K ; Grill, Alfred ; Koester, Steven J ; Ouyang, Qiqing ; Schaub, Jeremy D</creator><creatorcontrib>Chu, Jack O ; Dehlinger, Gabriel K ; Grill, Alfred ; Koester, Steven J ; Ouyang, Qiqing ; Schaub, Jeremy D ; International Business Machines Corporation</creatorcontrib><description>The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.</description><language>eng</language><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7915653$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7915653$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chu, Jack O</creatorcontrib><creatorcontrib>Dehlinger, Gabriel K</creatorcontrib><creatorcontrib>Grill, Alfred</creatorcontrib><creatorcontrib>Koester, Steven J</creatorcontrib><creatorcontrib>Ouyang, Qiqing</creatorcontrib><creatorcontrib>Schaub, Jeremy D</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><title>Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector</title><description>The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjE0KwjAQhbtxIeod5gIBpVRxXfzZiIu6l2kyaQJtJiST-xvBA7j6eLzvvXUzDpKKlpIILCfAYGAhcWyALVgck9coPkyA4PzkVI5EBvrHc1Cal1i7cSa4keKgfMhlRqk30bGwISFd07ZZWZwz7X7cNHC9vPq7KrnuKUh-Twm_2J_Oh-7Yte0fyge7Nj6g</recordid><startdate>20110329</startdate><enddate>20110329</enddate><creator>Chu, Jack O</creator><creator>Dehlinger, Gabriel K</creator><creator>Grill, Alfred</creator><creator>Koester, Steven J</creator><creator>Ouyang, Qiqing</creator><creator>Schaub, Jeremy D</creator><scope>EFH</scope></search><sort><creationdate>20110329</creationdate><title>Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector</title><author>Chu, Jack O ; Dehlinger, Gabriel K ; Grill, Alfred ; Koester, Steven J ; Ouyang, Qiqing ; Schaub, Jeremy D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_079156533</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Chu, Jack O</creatorcontrib><creatorcontrib>Dehlinger, Gabriel K</creatorcontrib><creatorcontrib>Grill, Alfred</creatorcontrib><creatorcontrib>Koester, Steven J</creatorcontrib><creatorcontrib>Ouyang, Qiqing</creatorcontrib><creatorcontrib>Schaub, Jeremy D</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chu, Jack O</au><au>Dehlinger, Gabriel K</au><au>Grill, Alfred</au><au>Koester, Steven J</au><au>Ouyang, Qiqing</au><au>Schaub, Jeremy D</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector</title><date>2011-03-29</date><risdate>2011</risdate><abstract>The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07915653 |
source | USPTO Issued Patents |
title | Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T10%3A40%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chu,%20Jack%20O&rft.aucorp=International%20Business%20Machines%20Corporation&rft.date=2011-03-29&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07915653%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |