Alternative method for advanced CMOS logic gate etch applications

Methods for etching, such as for fabricating a CMOS logic gate are provided herein. In some embodiments, a method of etching includes (a) providing a substrate having a first stack and a second stack disposed thereupon, the first stack comprising a high-k dielectric layer, a metal layer formed over...

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Bibliographische Detailangaben

Hauptverfasser:	Gani, Nicolas, Shen, Meihua, Deshmukh, Shashank
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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