Structure and method of forming a topside contact to a backside terminal of a semiconductor device

A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer exte...

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Hauptverfasser: Andrews, John T, Yilmaz, Hamza, Marchant, Bruce, Ho, Ihsiu
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Sprache:eng
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creator Andrews, John T
Yilmaz, Hamza
Marchant, Bruce
Ho, Ihsiu
description A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07884390</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07884390</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078843903</originalsourceid><addsrcrecordid>eNqNjEEKwjAQRbNxIeod5gJCoYJ1LZXu616myaQGm0xJJp7fRDyAq89_vP-3aholZi05EmAw4EmebIAtWI7ehRkQhNfkDIHmIKil9AIn1K8vFaoeLnWDkMi74plyyREMvZ2mvdpYXBIdfrlTcOvv1-GY04pCQdJjjlijOXfdqb007R_KB9PNPrE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Structure and method of forming a topside contact to a backside terminal of a semiconductor device</title><source>USPTO Issued Patents</source><creator>Andrews, John T ; Yilmaz, Hamza ; Marchant, Bruce ; Ho, Ihsiu</creator><creatorcontrib>Andrews, John T ; Yilmaz, Hamza ; Marchant, Bruce ; Ho, Ihsiu ; Fairchild Semiconductor Corporation</creatorcontrib><description>A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.</description><language>eng</language><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7884390$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7884390$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Andrews, John T</creatorcontrib><creatorcontrib>Yilmaz, Hamza</creatorcontrib><creatorcontrib>Marchant, Bruce</creatorcontrib><creatorcontrib>Ho, Ihsiu</creatorcontrib><creatorcontrib>Fairchild Semiconductor Corporation</creatorcontrib><title>Structure and method of forming a topside contact to a backside terminal of a semiconductor device</title><description>A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjEEKwjAQRbNxIeod5gJCoYJ1LZXu616myaQGm0xJJp7fRDyAq89_vP-3aholZi05EmAw4EmebIAtWI7ehRkQhNfkDIHmIKil9AIn1K8vFaoeLnWDkMi74plyyREMvZ2mvdpYXBIdfrlTcOvv1-GY04pCQdJjjlijOXfdqb007R_KB9PNPrE</recordid><startdate>20110208</startdate><enddate>20110208</enddate><creator>Andrews, John T</creator><creator>Yilmaz, Hamza</creator><creator>Marchant, Bruce</creator><creator>Ho, Ihsiu</creator><scope>EFH</scope></search><sort><creationdate>20110208</creationdate><title>Structure and method of forming a topside contact to a backside terminal of a semiconductor device</title><author>Andrews, John T ; Yilmaz, Hamza ; Marchant, Bruce ; Ho, Ihsiu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078843903</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Andrews, John T</creatorcontrib><creatorcontrib>Yilmaz, Hamza</creatorcontrib><creatorcontrib>Marchant, Bruce</creatorcontrib><creatorcontrib>Ho, Ihsiu</creatorcontrib><creatorcontrib>Fairchild Semiconductor Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Andrews, John T</au><au>Yilmaz, Hamza</au><au>Marchant, Bruce</au><au>Ho, Ihsiu</au><aucorp>Fairchild Semiconductor Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Structure and method of forming a topside contact to a backside terminal of a semiconductor device</title><date>2011-02-08</date><risdate>2011</risdate><abstract>A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. An epitaxial layer extends over the topside surface of the semiconductor substrate but terminates prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. An interconnect layer extends into the recessed region but terminates prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.</abstract><oa>free_for_read</oa></addata></record>
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title Structure and method of forming a topside contact to a backside terminal of a semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T06%3A16%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Andrews,%20John%20T&rft.aucorp=Fairchild%20Semiconductor%20Corporation&rft.date=2011-02-08&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07884390%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true