2-T SRAM cell structure and method

2-T SRAM cell structure and method

The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor i...

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Hauptverfasser: Liang, Qingqing, Rausch, Werner A, Zhu, Huilong
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Sprache:eng
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creator Liang, Qingqing
Rausch, Werner A
Zhu, Huilong
description The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.
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a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZFAy0g1RCA5y9FVITs3JUSguKSpNLiktSlVIzEtRyE0tychP4WFgTUvMKU7lhdLcDApuriHOHrqlxQWJJal5JcXx6UWJIMrA3MLCwMjYwpgIJQAJ9yXK</recordid><startdate>20110201</startdate><enddate>20110201</enddate><creator>Liang, Qingqing</creator><creator>Rausch, Werner A</creator><creator>Zhu, Huilong</creator><scope>EFH</scope></search><sort><creationdate>20110201</creationdate><title>2-T SRAM cell structure and method</title><author>Liang, Qingqing ; Rausch, Werner A ; Zhu, Huilong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078802383</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Liang, Qingqing</creatorcontrib><creatorcontrib>Rausch, Werner A</creatorcontrib><creatorcontrib>Zhu, Huilong</creatorcontrib><creatorcontrib>International Business Machines Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liang, Qingqing</au><au>Rausch, Werner A</au><au>Zhu, Huilong</au><aucorp>International Business Machines Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>2-T SRAM cell structure and method</title><date>2011-02-01</date><risdate>2011</risdate><abstract>The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, the second field effect transistor including a second active region present in the at least one device region of the substrate, the second active region including a second drain and a second source separated by a second channel region, wherein the second channel region includes a second trap that stores holes produced when the first field effect transistor is in the on state, wherein the holes stored in the second trap increase the second threshold voltage to be greater than the first threshold voltage.</abstract><oa>free_for_read</oa></addata></record>
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title 2-T SRAM cell structure and method
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