Method and apparatus for providing symmetrical output data for a double data rate DRAM

An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay...

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Bibliographische Detailangaben

Hauptverfasser:	Li, Wen, Schoenfeld, Aaron, Baker, R. Jacob
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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