Low power shift register and semiconductor memory device including the same

Low power shift register and semiconductor memory device including the same

A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in respon...

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1. Verfasser: Kim, Seung-Lo
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creator Kim, Seung-Lo
description A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07852687</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07852687</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078526873</originalsourceid><addsrcrecordid>eNqNykEKwjAQQNFsXIh6h7mAIIq2e1EEXbqXkEzTgWamZCYWb6-CB3D1-PDn7nqTCUaZsID21BkUTKT2Sc8RFDMF4ViDSYGMWcoLIj4pIBCHoUbiBNYjqM-4dLPOD4qrnwsH59P9eFlXHb0hmz5S8V82TbvfHtpm98fyBkciNrc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Low power shift register and semiconductor memory device including the same</title><source>USPTO Issued Patents</source><creator>Kim, Seung-Lo</creator><creatorcontrib>Kim, Seung-Lo ; Hynix Semiconductor Inc</creatorcontrib><description>A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7852687$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7852687$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kim, Seung-Lo</creatorcontrib><creatorcontrib>Hynix Semiconductor Inc</creatorcontrib><title>Low power shift register and semiconductor memory device including the same</title><description>A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNykEKwjAQQNFsXIh6h7mAIIq2e1EEXbqXkEzTgWamZCYWb6-CB3D1-PDn7nqTCUaZsID21BkUTKT2Sc8RFDMF4ViDSYGMWcoLIj4pIBCHoUbiBNYjqM-4dLPOD4qrnwsH59P9eFlXHb0hmz5S8V82TbvfHtpm98fyBkciNrc</recordid><startdate>20101214</startdate><enddate>20101214</enddate><creator>Kim, Seung-Lo</creator><scope>EFH</scope></search><sort><creationdate>20101214</creationdate><title>Low power shift register and semiconductor memory device including the same</title><author>Kim, Seung-Lo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078526873</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Kim, Seung-Lo</creatorcontrib><creatorcontrib>Hynix Semiconductor Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kim, Seung-Lo</au><aucorp>Hynix Semiconductor Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Low power shift register and semiconductor memory device including the same</title><date>2010-12-14</date><risdate>2010</risdate><abstract>A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.</abstract><oa>free_for_read</oa></addata></record>
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title Low power shift register and semiconductor memory device including the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-10T17%3A59%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kim,%20Seung-Lo&rft.aucorp=Hynix%20Semiconductor%20Inc&rft.date=2010-12-14&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07852687%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true