Capacitors and methods of manufacture thereof

Capacitors and methods of manufacture thereof

Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in ar...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Hierlemann, Matthias
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Hierlemann, Matthias
description Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07851302</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07851302</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078513023</originalsourceid><addsrcrecordid>eNrjZNB1TixITM4syS8qVkjMS1HITS3JyE8pVshPU8hNzCtNS0wuKS1KVSjJSC1KzU_jYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcwtTQ2MDImAglAKbpKyM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Capacitors and methods of manufacture thereof</title><source>USPTO Issued Patents</source><creator>Hierlemann, Matthias</creator><creatorcontrib>Hierlemann, Matthias ; Infineon Technologies AG</creatorcontrib><description>Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7851302$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7851302$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hierlemann, Matthias</creatorcontrib><creatorcontrib>Infineon Technologies AG</creatorcontrib><title>Capacitors and methods of manufacture thereof</title><description>Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZNB1TixITM4syS8qVkjMS1HITS3JyE8pVshPU8hNzCtNS0wuKS1KVSjJSC1KzU_jYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcwtTQ2MDImAglAKbpKyM</recordid><startdate>20101214</startdate><enddate>20101214</enddate><creator>Hierlemann, Matthias</creator><scope>EFH</scope></search><sort><creationdate>20101214</creationdate><title>Capacitors and methods of manufacture thereof</title><author>Hierlemann, Matthias</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078513023</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Hierlemann, Matthias</creatorcontrib><creatorcontrib>Infineon Technologies AG</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hierlemann, Matthias</au><aucorp>Infineon Technologies AG</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Capacitors and methods of manufacture thereof</title><date>2010-12-14</date><risdate>2010</risdate><abstract>Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07851302
source USPTO Issued Patents
title Capacitors and methods of manufacture thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T12%3A33%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Hierlemann,%20Matthias&rft.aucorp=Infineon%20Technologies%20AG&rft.date=2010-12-14&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07851302%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true