Integrated circuit having ultralow-K dielectric layer

A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to s...

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Bibliographische Detailangaben

Hauptverfasser:	Widodo, Johnny, Liu, Huang, Lim, Sin Leng
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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