Integrated circuit having ultralow-K dielectric layer

Integrated circuit having ultralow-K dielectric layer

A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to s...

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Hauptverfasser: Widodo, Johnny, Liu, Huang, Lim, Sin Leng
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Sprache:eng
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creator Widodo, Johnny
Liu, Huang
Lim, Sin Leng
description A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect the device layer from exposure to subsequently processing, such as curing medium used to form voids in an ultralow-k dielectric layer.
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title Integrated circuit having ultralow-K dielectric layer
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