Linearized digital phase-locked loop method for maintaining end of packet time linearity

An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock...

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Bibliographische Detailangaben

Hauptverfasser:	Prather, Stephen M, Berzins, Matthew S, Cornell, Charles A, Larky, Steven P, Cetin, Joseph A
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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