Test structures and methods
Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Marokkey, Sajan |
| description | Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece. |
| format | Patent |
| fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07820458</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07820458</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078204583</originalsourceid><addsrcrecordid>eNrjZJAOSS0uUSguKSpNLiktSi1WSMxLUchNLcnITynmYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcwsjAxNTCmAglAG7OJH8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Test structures and methods</title><source>USPTO Issued Patents</source><creator>Marokkey, Sajan</creator><creatorcontrib>Marokkey, Sajan ; Infineon Technologies AG</creatorcontrib><description>Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7820458$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64039</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7820458$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Marokkey, Sajan</creatorcontrib><creatorcontrib>Infineon Technologies AG</creatorcontrib><title>Test structures and methods</title><description>Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZJAOSS0uUSguKSpNLiktSi1WSMxLUchNLcnITynmYWBNS8wpTuWF0twMCm6uIc4euqXFBYklqXklxfHpRYkgysDcwsjAxNTCmAglAG7OJH8</recordid><startdate>20101026</startdate><enddate>20101026</enddate><creator>Marokkey, Sajan</creator><scope>EFH</scope></search><sort><creationdate>20101026</creationdate><title>Test structures and methods</title><author>Marokkey, Sajan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078204583</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Marokkey, Sajan</creatorcontrib><creatorcontrib>Infineon Technologies AG</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Marokkey, Sajan</au><aucorp>Infineon Technologies AG</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Test structures and methods</title><date>2010-10-26</date><risdate>2010</risdate><abstract>Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_uspatents_grants_07820458 |
| source | USPTO Issued Patents |
| title | Test structures and methods |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T11%3A18%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Marokkey,%20Sajan&rft.aucorp=Infineon%20Technologies%20AG&rft.date=2010-10-26&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07820458%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |